Atmel ATmega328P Xplained Mini MEGA328P-XMINI MEGA328P-XMINI Data Sheet
Product codes
MEGA328P-XMINI
231
ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
Atmel-8271H-AVR- ATmega-Datasheet_08/2014
Figure 22-21. Possible Status Codes Caused by Arbitration
22.9
Register Description
22.9.1 TWBR – TWI Bit Rate Register
• Bits 7...0 – TWI Bit Rate Register
TWBR selects the division factor for the bit rate generator. The bit rate generator is a frequency divider which
generates the SCL clock frequency in the Master modes. See
generates the SCL clock frequency in the Master modes. See
calculating bit rates.
22.9.2 TWCR – TWI Control Register
The TWCR is used to control the operation of the TWI. It is used to enable the TWI, to initiate a Master access
by applying a START condition to the bus, to generate a Receiver acknowledge, to generate a stop condition,
and to control halting of the bus while the data to be written to the bus are written to the TWDR. It also indicates
a write collision if data is attempted written to TWDR while the register is inaccessible.
by applying a START condition to the bus, to generate a Receiver acknowledge, to generate a stop condition,
and to control halting of the bus while the data to be written to the bus are written to the TWDR. It also indicates
a write collision if data is attempted written to TWDR while the register is inaccessible.
• Bit 7 – TWINT: TWI Interrupt Flag
This bit is set by hardware when the TWI has finished its current job and expects application software response.
If the I-bit in SREG and TWIE in TWCR are set, the MCU will jump to the TWI Interrupt Vector. While the TWINT
Flag is set, the SCL low period is stretched. The TWINT Flag must be cleared by software by writing a logic one
to it. Note that this flag is not automatically cleared by hardware when executing the interrupt routine. Also note
that clearing this flag starts the operation of the TWI, so all accesses to the TWI Address Register (TWAR), TWI
Status Register (TWSR), and TWI Data Register (TWDR) must be complete before clearing this flag.
If the I-bit in SREG and TWIE in TWCR are set, the MCU will jump to the TWI Interrupt Vector. While the TWINT
Flag is set, the SCL low period is stretched. The TWINT Flag must be cleared by software by writing a logic one
to it. Note that this flag is not automatically cleared by hardware when executing the interrupt routine. Also note
that clearing this flag starts the operation of the TWI, so all accesses to the TWI Address Register (TWAR), TWI
Status Register (TWSR), and TWI Data Register (TWDR) must be complete before clearing this flag.
Own
Address / General Call
received
Arbitration lost in SLA
TWI bus will be released and not addressed slave mode will be entered
A START condition will be transmitted when the bus becomes free
A START condition will be transmitted when the bus becomes free
No
Arbitration lost in Data
Direction
Yes
Write
Data byte will be received and NOT ACK will be returned
Data byte will be received and ACK will be returned
Data byte will be received and ACK will be returned
Last data byte will be transmitted and NOT ACK should be received
Data byte will be transmitted and ACK should be received
Data byte will be transmitted and ACK should be received
Read
B0
68/78
38
SLA
START
Data
STOP
Bit
7
6
5
4
3
2
1
0
TWBR7
TWBR6
TWBR5
TWBR4
TWBR3
TWBR2
TWBR1
TWBR0
TWBR
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
TWINT
TWEA
TWSTA
TWSTO
TWWC
TWEN
–
TWIE
TWCR
Read/Write
R/W
R/W
R/W
R/W
R
R/W
R
R/W
Initial Value
0
0
0
0
0
0
0
0