Atmel ATmega328P Xplained Mini MEGA328P-XMINI MEGA328P-XMINI Data Sheet
Product codes
MEGA328P-XMINI
240
ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
Atmel-8271H-AVR- ATmega-Datasheet_08/2014
The ADC has its own interrupt which can be triggered when a conversion completes. When ADC access to the
Data Registers is prohibited between reading of ADCH and ADCL, the interrupt will trigger even if the result is
lost.
Data Registers is prohibited between reading of ADCH and ADCL, the interrupt will trigger even if the result is
lost.
24.3
Starting a Conversion
A single conversion is started by disabling the Power Reduction ADC bit, PRADC, in
by writing a logical zero to it and writing a logical one to the ADC Start Conversion bit,
ADSC. This bit stays high as long as the conversion is in progress and will be cleared by hardware when the
conversion is completed. If a different data channel is selected while a conversion is in progress, the ADC will
finish the current conversion before performing the channel change.
conversion is completed. If a different data channel is selected while a conversion is in progress, the ADC will
finish the current conversion before performing the channel change.
Alternatively, a conversion can be triggered automatically by various sources. Auto Triggering is enabled by
setting the ADC Auto Trigger Enable bit, ADATE in ADCSRA. The trigger source is selected by setting the ADC
Trigger Select bits, ADTS in ADCSRB (See description of the ADTS bits for a list of the trigger sources). When
a positive edge occurs on the selected trigger signal, the ADC prescaler is reset and a conversion is started.
This provides a method of starting conversions at fixed intervals. If the trigger signal still is set when the
conversion completes, a new conversion will not be started. If another positive edge occurs on the trigger signal
during conversion, the edge will be ignored. Note that an Interrupt Flag will be set even if the specific interrupt is
disabled or the Global Interrupt Enable bit in SREG is cleared. A conversion can thus be triggered without
causing an interrupt. However, the Interrupt Flag must be cleared in order to trigger a new conversion at the
next interrupt event.
setting the ADC Auto Trigger Enable bit, ADATE in ADCSRA. The trigger source is selected by setting the ADC
Trigger Select bits, ADTS in ADCSRB (See description of the ADTS bits for a list of the trigger sources). When
a positive edge occurs on the selected trigger signal, the ADC prescaler is reset and a conversion is started.
This provides a method of starting conversions at fixed intervals. If the trigger signal still is set when the
conversion completes, a new conversion will not be started. If another positive edge occurs on the trigger signal
during conversion, the edge will be ignored. Note that an Interrupt Flag will be set even if the specific interrupt is
disabled or the Global Interrupt Enable bit in SREG is cleared. A conversion can thus be triggered without
causing an interrupt. However, the Interrupt Flag must be cleared in order to trigger a new conversion at the
next interrupt event.
Figure 24-2.
ADC Auto Trigger Logic
Using the ADC Interrupt Flag as a trigger source makes the ADC start a new conversion as soon as the ongoing
conversion has finished. The ADC then operates in Free Running mode, constantly sampling and updating the
ADC Data Register. The first conversion must be started by writing a logical one to the ADSC bit in ADCSRA. In
this mode the ADC will perform successive conversions independently of whether the ADC Interrupt Flag, ADIF
is cleared or not.
conversion has finished. The ADC then operates in Free Running mode, constantly sampling and updating the
ADC Data Register. The first conversion must be started by writing a logical one to the ADSC bit in ADCSRA. In
this mode the ADC will perform successive conversions independently of whether the ADC Interrupt Flag, ADIF
is cleared or not.
If Auto Triggering is enabled, single conversions can be started by writing ADSC in ADCSRA to one. ADSC can
also be used to determine if a conversion is in progress. The ADSC bit will be read as one during a conversion,
independently of how the conversion was started.
also be used to determine if a conversion is in progress. The ADSC bit will be read as one during a conversion,
independently of how the conversion was started.
ADSC
ADIF
SOURCE 1
SOURCE n
ADTS[2:0]
CONVERSION
LOGIC
PRESCALER
START
CLK
ADC
.
.
.
.
.
.
.
EDGE
DETECTOR
ADATE