Atmel ATmega328P Xplained Mini MEGA328P-XMINI MEGA328P-XMINI Data Sheet
Product codes
MEGA328P-XMINI
262
ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
Atmel-8271H-AVR- ATmega-Datasheet_08/2014
26.3
Register Description
26.3.1 SPMCSR – Store Program Memory Control and Status Register
The Store Program Memory Control and Status Register contains the control bits needed to control the Program
memory operations.
memory operations.
• Bit 7 – SPMIE: SPM Interrupt Enable
When the SPMIE bit is written to one, and the I-bit in the Status Register is set (one), the SPM ready interrupt
will be enabled. The SPM ready Interrupt will be executed as long as the SPMEN bit in the SPMCSR Register is
cleared. The interrupt will not be generated during EEPROM write or SPM.
will be enabled. The SPM ready Interrupt will be executed as long as the SPMEN bit in the SPMCSR Register is
cleared. The interrupt will not be generated during EEPROM write or SPM.
• Bit 6 – RWWSB: Read-While-Write Section Busy
This bit is for compatibility with devices supporting Read-While-Write. It will always read as zero in ATmega
48A/48PA.
48A/48PA.
• Bit 5 – SIGRD: Signature Row Read
If this bit is written to one at the same time as SPMEN, the next LPM instruction within three clock cycles will
read a byte from the signature row into the destination register. see
read a byte from the signature row into the destination register. see
for details. An SPM instruction within four cycles after SIGRD and SPMEN are set will have no
effect. This operation is reserved for future use and should not be used.
• Bit 4 – RWWSRE: Read-While-Write Section Read Enable
The functionality of this bit in ATmega 48A/48PA is a subset of the functionality in
ATmega88A/88PA/168A/168PA/328/328P. If the RWWSRE bit is written while filling the temporary page buffer,
the temporary page buffer will be cleared and the data will be lost.
ATmega88A/88PA/168A/168PA/328/328P. If the RWWSRE bit is written while filling the temporary page buffer,
the temporary page buffer will be cleared and the data will be lost.
• Bit 3 – BLBSET: Boot Lock Bit Set
The functionality of this bit in ATmega 48A/48PA is a subset of the functionality in
ATmega88A/88PA/168A/168PA/328/328P. An LPM instruction within three cycles after BLBSET and SPMEN
are set in the SPMCSR Register, will read either the Lock bits or the Fuse bits (depending on Z0 in the Z-
pointer) into the destination register. See
ATmega88A/88PA/168A/168PA/328/328P. An LPM instruction within three cycles after BLBSET and SPMEN
are set in the SPMCSR Register, will read either the Lock bits or the Fuse bits (depending on Z0 in the Z-
pointer) into the destination register. See
for
details.
• Bit 2 – PGWRT: Page Write
If this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock cycles
executes Page Write, with the data stored in the temporary buffer. The page address is taken from the high part
of the Z-pointer. The data in R1 and R0 are ignored. The PGWRT bit will auto-clear upon completion of a Page
Write, or if no SPM instruction is executed within four clock cycles. The CPU is halted during the entire Page
Write operation.
executes Page Write, with the data stored in the temporary buffer. The page address is taken from the high part
of the Z-pointer. The data in R1 and R0 are ignored. The PGWRT bit will auto-clear upon completion of a Page
Write, or if no SPM instruction is executed within four clock cycles. The CPU is halted during the entire Page
Write operation.
• Bit 1 – PGERS: Page Erase
If this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock cycles
executes Page Erase. The page address is taken from the high part of the Z-pointer. The data in R1 and R0 are
executes Page Erase. The page address is taken from the high part of the Z-pointer. The data in R1 and R0 are
Bit
7
6
5
4
3
2
1
0
SPMIE
RWWSB
SIGRD
RWWSRE
BLBSET
PGWRT
PGERS
SPMEN
SPMCSR
Read/Write
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0