Atmel ATmega328P Xplained Mini MEGA328P-XMINI MEGA328P-XMINI Data Sheet
Product codes
MEGA328P-XMINI
279
ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
Atmel-8271H-AVR- ATmega-Datasheet_08/2014
27.9
Register Description
27.9.1 SPMCSR – Store Program Memory Control and Status Register
The Store Program Memory Control and Status Register contains the control bits needed to control the Boot
Loader operations.
Loader operations.
• Bit 7 – SPMIE: SPM Interrupt Enable
When the SPMIE bit is written to one, and the I-bit in the Status Register is set (one), the SPM ready interrupt
will be enabled. The SPM ready Interrupt will be executed as long as the SPMEN bit in the SPMCSR Register is
cleared.
will be enabled. The SPM ready Interrupt will be executed as long as the SPMEN bit in the SPMCSR Register is
cleared.
• Bit 6 – RWWSB: Read-While-Write Section Busy
When a Self-Programming (Page Erase or Page Write) operation to the RWW section is initiated, the RWWSB
will be set (one) by hardware. When the RWWSB bit is set, the RWW section cannot be accessed. The
RWWSB bit will be cleared if the RWWSRE bit is written to one after a Self-Programming operation is
completed. Alternatively the RWWSB bit will automatically be cleared if a page load operation is initiated.
will be set (one) by hardware. When the RWWSB bit is set, the RWW section cannot be accessed. The
RWWSB bit will be cleared if the RWWSRE bit is written to one after a Self-Programming operation is
completed. Alternatively the RWWSB bit will automatically be cleared if a page load operation is initiated.
• Bit 5 – SIGRD: Signature Row Read
If this bit is written to one at the same time as SPMEN, the next LPM instruction within three clock cycles will
read a byte from the signature row into the destination register. see
read a byte from the signature row into the destination register. see
for details. An SPM instruction within four cycles after SIGRD and SPMEN are set will have no
effect. This operation is reserved for future use and should not be used.
• Bit 4 – RWWSRE: Read-While-Write Section Read Enable
When programming (Page Erase or Page Write) to the RWW section, the RWW section is blocked for reading
(the RWWSB will be set by hardware). To re-enable the RWW section, the user software must wait until the
programming is completed (SPMEN will be cleared). Then, if the RWWSRE bit is written to one at the same
time as SPMEN, the next SPM instruction within four clock cycles re-enables the RWW section. The RWW
section cannot be re-enabled while the Flash is busy with a Page Erase or a Page Write (SPMEN is set). If the
RWWSRE bit is written while the Flash is being loaded, the Flash load operation will abort and the data loaded
will be lost.
(the RWWSB will be set by hardware). To re-enable the RWW section, the user software must wait until the
programming is completed (SPMEN will be cleared). Then, if the RWWSRE bit is written to one at the same
time as SPMEN, the next SPM instruction within four clock cycles re-enables the RWW section. The RWW
section cannot be re-enabled while the Flash is busy with a Page Erase or a Page Write (SPMEN is set). If the
RWWSRE bit is written while the Flash is being loaded, the Flash load operation will abort and the data loaded
will be lost.
• Bit 3 – BLBSET: Boot Lock Bit Set
If this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock cycles sets
Boot Lock bits and Memory Lock bits, according to the data in R0. The data in R1 and the address in the Z-
pointer are ignored. The BLBSET bit will automatically be cleared upon completion of the Lock bit set, or if no
SPM instruction is executed within four clock cycles.
Boot Lock bits and Memory Lock bits, according to the data in R0. The data in R1 and the address in the Z-
pointer are ignored. The BLBSET bit will automatically be cleared upon completion of the Lock bit set, or if no
SPM instruction is executed within four clock cycles.
An LPM instruction within three cycles after BLBSET and SPMEN are set in the SPMCSR Register, will read
either the Lock bits or the Fuse bits (depending on Z0 in the Z-pointer) into the destination register. See
either the Lock bits or the Fuse bits (depending on Z0 in the Z-pointer) into the destination register. See
for details.
• Bit 2 – PGWRT: Page Write
If this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock cycles
executes Page Write, with the data stored in the temporary buffer. The page address is taken from the high part
of the Z-pointer. The data in R1 and R0 are ignored. The PGWRT bit will auto-clear upon completion of a Page
executes Page Write, with the data stored in the temporary buffer. The page address is taken from the high part
of the Z-pointer. The data in R1 and R0 are ignored. The PGWRT bit will auto-clear upon completion of a Page
Bit
7
6
5
4
3
2
1
0
SPMIE
RWWSB
SIGRD
RWWSRE
BLBSET
PGWRT
PGERS
SPMEN
SPMCSR
Read/Write
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0