Atmel ATmega328P Xplained Mini MEGA328P-XMINI MEGA328P-XMINI Data Sheet

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ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]

Atmel-8271H-AVR- ATmega-Datasheet_08/2014

This section discusses the AVR core architecture in general. The main function of the CPU core is to ensure 
correct program execution. The CPU must therefore be able to access memories, perform calculations, control 
peripherals, and handle interrupts.

Block Diagram of the AVR Architecture 

In order to maximize performance and parallelism, the AVR uses a Harvard architecture – with separate 
memories and buses for program and data. Instructions in the program memory are executed with a single level 
pipelining. While one instruction is being executed, the next instruction is pre-fetched from the program memory. 
This concept enables instructions to be executed in every clock cycle. The program memory is In-System 
Reprogrammable Flash memory.

The fast-access Register File contains 32 x 8-bit general purpose working registers with a single clock cycle 
access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typical ALU operation, two 

Flash

Program

Memory

Instruction

Register

Instruction

Decoder

Program

Counter

Control Lines

32 x 8

General

Purpose

Registrers

ALU

Status

and Control

I/O Lines

EEPROM

Data Bus 8-bit

 

Data

SRAM

Direct Addressing

Indirect Addressing

Interrupt

Unit

SPI

Unit

Watchdog

Timer

Analog

Comparator

I/O Module 2

I/O Module1

I/O Module n