Atmel ATmega328P Xplained Mini MEGA328P-XMINI MEGA328P-XMINI Data Sheet
Product codes
MEGA328P-XMINI
98
ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
Atmel-8271H-AVR- ATmega-Datasheet_08/2014
Be aware that the COM0x1:0 bits are not double buffered together with the compare value. Changing the
COM0x1:0 bits will take effect immediately.
COM0x1:0 bits will take effect immediately.
15.6
Compare Match Output Unit
The Compare Output mode (COM0x1:0) bits have two functions. The Waveform Generator uses the COM0x1:0
bits for defining the Output Compare (OC0x) state at the next compare match. Also, the COM0x1:0 bits control
the OC0x pin output source.
bits for defining the Output Compare (OC0x) state at the next compare match. Also, the COM0x1:0 bits control
the OC0x pin output source.
shows a simplified schematic of the logic affected by the COM0x1:0 bit
setting. The I/O Registers, I/O bits, and I/O pins in the figure are shown in bold. Only the parts of the general I/O
port control registers (DDR and PORT) that are affected by the COM0x1:0 bits are shown. When referring to the
OC0x state, the reference is for the internal OC0x Register, not the OC0x pin. If a system reset occur, the OC0x
Register is reset to “0”.
port control registers (DDR and PORT) that are affected by the COM0x1:0 bits are shown. When referring to the
OC0x state, the reference is for the internal OC0x Register, not the OC0x pin. If a system reset occur, the OC0x
Register is reset to “0”.
Figure 15-4.
Compare Match Output Unit, Schematic
The general I/O port function is overridden by the Output Compare (OC0x) from the Waveform Generator if
either of the COM0x1:0 bits are set. However, the OC0x pin direction (input or output) is still controlled by the
Data Direction Register (DDR) for the port pin. The Data Direction Register bit for the OC0x pin (DDR_OC0x)
must be set as output before the OC0x value is visible on the pin. The port override function is independent of
the Waveform Generation mode.
either of the COM0x1:0 bits are set. However, the OC0x pin direction (input or output) is still controlled by the
Data Direction Register (DDR) for the port pin. The Data Direction Register bit for the OC0x pin (DDR_OC0x)
must be set as output before the OC0x value is visible on the pin. The port override function is independent of
the Waveform Generation mode.
The design of the Output Compare pin logic allows initialization of the OC0x state before the output is enabled.
Note that some COM0x1:0 bit settings are reserved for certain modes of operation. See
Note that some COM0x1:0 bit settings are reserved for certain modes of operation. See
15.6.1 Compare Output Mode and Waveform Generation
The Waveform Generator uses the COM0x1:0 bits differently in Normal, CTC, and PWM modes. For all modes,
setting the COM0x1:0 = 0 tells the Waveform Generator that no action on the OC0x Register is to be performed
on the next compare match. For compare output actions in the non-PWM modes refer to
setting the COM0x1:0 = 0 tells the Waveform Generator that no action on the OC0x Register is to be performed
on the next compare match. For compare output actions in the non-PWM modes refer to
. For fast PWM mode, refer to
, and for phase correct PWM refer to
A change of the COM0x1:0 bits state will have effect at the first compare match after the bits are written. For
non-PWM modes, the action can be forced to have immediate effect by using the FOC0x strobe bits.
non-PWM modes, the action can be forced to have immediate effect by using the FOC0x strobe bits.
PORT
DDR
D
Q
D
Q
OCnx
Pin
OCnx
D
Q
Waveform
Generator
COMnx1
COMnx0
0
1
DA
T
A
B
U
S
FOCn
clk
I/O