Taskit ARM9 CPU-module with Linux Stamp9261-series Stamp9261 (64F/64R) 542310 Data Sheet
Product codes
542310
4.13. LCD Controller (LCDC)
The LCD Controller of the SAM9261 processor (theoretically) supports displays with a resolution up to
2048x2048 pixels with a color depth of 24 bit per pixel, or 8 bit per color. To implement a fitting LCD,
glue hardware is necessary.
2048x2048 pixels with a color depth of 24 bit per pixel, or 8 bit per color. To implement a fitting LCD,
glue hardware is necessary.
The LCD controller relies on a relatively simple frame buffer concept, which means that all graphics
and character functions have to be implemented in software: character sets and graphic primitives are
not integrated in the controller.
and character functions have to be implemented in software: character sets and graphic primitives are
not integrated in the controller.
a) LCDC Initialization and LCD Power Sequencing
LCD cells (pixels) should not be subjected to DC power for prolonged periods of time, as chemical
decomposition might take place. The LCD controller therefore provides for a strict AC control of the
LCD pixels. To do so, the LCD controller has to be initialized appropriately. Switching on the LCD
supply voltage therefore has to take place after the LCDC initialization or shortly before.
LCD cells (pixels) should not be subjected to DC power for prolonged periods of time, as chemical
decomposition might take place. The LCD controller therefore provides for a strict AC control of the
LCD pixels. To do so, the LCD controller has to be initialized appropriately. Switching on the LCD
supply voltage therefore has to take place after the LCDC initialization or shortly before.
Accordingly, the LCDC should not be powered down without deactivating the LCD supply voltage. The
same is true if the LCDC is stopped indirectly by stopping the respective clock source, namely the
PLLA.
same is true if the LCDC is stopped indirectly by stopping the respective clock source, namely the
PLLA.
The LCD backlight supply is not involved in these considerations. It may switched on or off at any time
independently of the state of the LCDC.
independently of the state of the LCDC.
b) LCDC Video Memory Selection
The video memory of the LCDC is part of the working memory of the processor. It might either reside
in the internal SRAM, as well as in the external SDRAM. Using the internal SRAM has the advantage
that the LCDC can access its video memory via an autonomous bus and does not affect the processor
performance. However, as the internal SRAM has a capacity of only 160 KBytes, the color depth for a
QVGA display is only 16 bit / pixel (320 x 240 x 2 = 153600 bytes are necessary). For a high quality
display 16 bit per pixel might not be sufficient.
The video memory of the LCDC is part of the working memory of the processor. It might either reside
in the internal SRAM, as well as in the external SDRAM. Using the internal SRAM has the advantage
that the LCDC can access its video memory via an autonomous bus and does not affect the processor
performance. However, as the internal SRAM has a capacity of only 160 KBytes, the color depth for a
QVGA display is only 16 bit / pixel (320 x 240 x 2 = 153600 bytes are necessary). For a high quality
display 16 bit per pixel might not be sufficient.
On the other hand, using the SDRAM as video memory has the advantage that there is plenty of
space for all resolutions. Also the internal SRAM is now available for time critical software sections. Of
course the LCDC will now be permanently scanning its video memory and might therefore reduce the
overall performance to some degree.
space for all resolutions. Also the internal SRAM is now available for time critical software sections. Of
course the LCDC will now be permanently scanning its video memory and might therefore reduce the
overall performance to some degree.
c) LCDC Frame Buffer
The LCDC video memory is organized as a frame buffer in a straight forward way. It supports color
depths of 1, 2, 4, 8, 16, or 24 bit per pixel. The video data is stored in a packed form with no unused
bits in the video memory.
The LCDC video memory is organized as a frame buffer in a straight forward way. It supports color
depths of 1, 2, 4, 8, 16, or 24 bit per pixel. The video data is stored in a packed form with no unused
bits in the video memory.
The color resolutions of 1, 2, 4, and 8 bpp (bits per pixel) use a palette table which is made up of 16-bit
entries. The value of each pixel in the frame buffer serves as an index into the palette table. The value
of the respective palette table entry is output to the display by the LCDC.
entries. The value of each pixel in the frame buffer serves as an index into the palette table. The value
of the respective palette table entry is output to the display by the LCDC.
Each palette table entry has the form
Bit 15
Bit[14..10]
Bit[9..5]
Bit[4..0]
Intensity Bit
Blue[7..3]
Green[7..3]
Red[7..3]
The bits 2..0 of each color channel are not used in the palletized configuration – they are set to zero.
The intensity bit sets the least significant valid bits of every color, that is, the bits 2, 10, and 18 of a 24-
bit LCDC output word.
The intensity bit sets the least significant valid bits of every color, that is, the bits 2, 10, and 18 of a 24-
bit LCDC output word.
The same scheme as above is used in the 16-bit color resolution configuration, although in this case
the frame buffer entry is output directly to the display instead of indexing a palette table.
the frame buffer entry is output directly to the display instead of indexing a palette table.
In the 24-bit color resolution configuration, each frame buffer entry consists of one byte for each color:
Bit[23..16]
Bit[15..8]
Bit[7..0]
Blue[7..0]
Green[7..0]
Red[7..0]
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