Intel E3815 FH8065301567411 Data Sheet

Intel

®

 Atom™ Processor E3800 Product Family

1002

Datasheet

23

0b

RW

Reserved.

22

0b

RW

When used as a sprite in the 16/32-bpp modes 

without alpha this enables source color keying. Sprite pixel values that match (within 

range) the key will become transparent. Setting this bit is not allowed when the Sprite D 

pixel format includes an alpha channel. 

[DevBW] Erratum: This bit must always be set to 0 when Sprite D pixel format is YUV 

0 = Sprite source key is disabled (default) 

1 = Sprite source key is enabled.

21:20

0b

RW

This cause the display plane to duplicate lines and pixels sent to 

the assigned pipe. In the line/pixel doubling mode, the horizontal pixels are doubled and 

lines are sent twice. This is a method of scaling the source image by two (both H and V). 

00 = No line/Pixel duplication 

01 = Line/Pixel Doubling 

10 = Line Doubling only 

11 = Pixel Doubling only

19

0b

RW

This bit enables or disables the color conversion 

logic. Color conversion is intended to be used with the formats that support YUV formats 

such as the YUV 4:2:2 packed format and x:8:8:8 and 8:8:8:8 formats. Formats such 

as RGB5:5:5 and 5:6:5 do not have YUV versions.  

0 = Pixel data is sent through the conversion logic (only applies to YUV formats) 

1 = Pixel data is not sent through the YUV-)RGB conversion logic.

18

0b

RW

This bit specifies the source YUV format for the YUV to RGB color 

conversion operation. This field is ignored when source data is RGB. 

0 = ITU-R Recommendation BT.601 

1 = ITU-R Recommendation BT.709

17:16

0b

RW

This field is used to select the byte order when using YUV 4:2:2 

data formats. For other formats, this field is ignored.  

00 = YUYV 

01 = UYVY 

10 = YVYU 

11 = VYUY

15

0b

RW

This mode causes the display plane to be rotated 180 . In 

addition to setting this bit, software must also set the base address to the lower right 

corner of the unrotated image and calculate the x, y offset as relative to the lower right 

corner. 

0 = No rotation 

1 = 180 rotation

14:11

0b

RW

Reserved.

10

0b

RW

This bit indicates that the Sprite D surface data is in tiled memory. 

The tile pitch is specified in bytes in the DSPCSTRIDE register. Only X tiling is supported 

for display surfaces. 

When this bit is set, it affects the hardware interpretation of the DSPCTILEOFF, 

DSPCLINOFF, and DSPCSURFADDR registers. 

0 = Sprite D surface uses linear memory 

1 = Sprite D surface uses X-tiled memory

9:3

0b

RW

Write as zero

2

0b

RW

This bit will force the Sprite D plane to be on the bottom of the Z 

order. If the plane is marked as trusted, it only applies to the Z order of the trusted 

planes. 

0 = Sprite D Z order is determined by the other control bits 

1 = Sprite D is forced to be on the bottom of the Z order.

1

0b

RW

Reserved.