Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
1008
Datasheet
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SPRITE
_
D
_SURF
A
C
E
_BASE_ADDRE
S
S
RE
SE
RVED
FLIP_SO
U
RCE
DE
CR
YPTION_REQ
UEST
RESE
RVED
_1
Bit
Range
Default &
Access
Field Name (ID): Description
31:12
0b
RW
SPRITE_D_SURFACE_BASE_ADDRESS:
This address specifies the surface base
address. When the surface is tiled, panning is specified using (x, y) offsets in the
DSPCTILEOFF register. When the surface is in linear memory, panning is specified using
a linear offset in the DSPCLINOFF register.
This address must be 4K aligned. This register can be written directly through software
or by command packets in the command stream. It represents an offset from the
graphics memory aperture base and is mapped to physical pages through the global
GTT.
If the device supports trusted operation and this plane is not marked trusted, the
memory pages must not be marked NoDMA .
The value in this register is updated through the command streamer during
synchronous flips.
[DevBW] and [DevCL]: This address must be 128K aligned for linear memory.
11:4
0b
RW
RESERVED:
: MBZ
3
0b
RW
FLIP_SOURCE:
Project:
All
Default Value:
0b
This bit indicates if the source of the flip is CS or BCS so display can send the flip done
response to the appropriate destination.
ValueNameDescriptionProject
0b
CS
Flip source is CS
All
1b
BCS
Flip source is BCS
All