Intel E3815 FH8065301567411 Data Sheet

Product codes

FH8065301567411

Power Up and Reset Sequence

Intel

Atom™ Processor E3800 Product Family

Datasheet

101

NOTES:.

RTC and SUS power rails may come up at the same time if no RTC battery is used.

Must ensure RTC clock is oscillating before these counts. SoC counts this time assuming a RTC clock of

32.768 KHz. Depending on how stable the oscillations are, however, this time can vary (+/-). This is

effectively the typical amount of time the SoC waits to help ensure the clock is stable enough to proceed

with power sequencing. It’s more likely a min since RTC clock will typically run slow until stable.

Wake events shown in figure depend on platform configuration.

In the SUS rail sequence, V3P3A can be first in sequence if required for designs, otherwise it can end

the SUS sequence.

An alternate SUS rail sequence allows swapping V1P8A with V1P0A.

For power rail sequences, at least 10us delay is required between rails to avoid inrush current caused by

multiple loads turning on simultaneously and fast charging of VR output decoupling. A maximum delay

of 2 ms is allowed. Measurement of delay is at the 90% of full voltage mark of the prior rail to 10% later

rail.

VCC can follow VNN in the CORE rail sequence or at the same time. Reference platform sequences both

at the same time.

“Board Event” is platform specific. Most likely enabled by a platform power management controller or

PMIC via a dedicated power button or when AC power is applied.

For exit from S4 and S3 Events, see “Cause of Wake Events” table in this chapter. S4 wake is required

from PMC_PWRBTN# without prior configuration. S3 wake event is only used when the platform directly

transitions to S3 (STR).

10.

The V1P35S rail “VGA_V1P35_S3_F1” must be powered on as shown above. All other V1P35S/VSFR

([X]_V1P35_S3_F[x]) rails can either power on as shown, or power on after V3P3S.

11.

PMC_SUSPWRDNACK is intended to be used at power-down and, since its state after a power-down is

variable, it is recommended that a system treats PMC_SUSRWRDNACK as a Do Not Care during power-

on. For systems that are unable to treat PMC_SUSPWRDNACK as a Do Not Care during power-on, the

following power-on state is always valid: - 1) PMC_SUSPWRDNACK will always be low, until

PMC_SLP_S3# de-asserts, if PMC_SUSPWRDNACK was low upon entry into S5. PMC_SUSPWRDNACK is

always low when entering S5 from G3.

12.

Where no maximum timing is specified, it is expected that the maximum timing should typically be

within one unit of time of the minimum timing, under normal operating conditions. Due to potential

variability in operating conditions, no maximum timing can be guaranteed however.

13.

When HDA_LPE_V1P5V1P8_S3 is powered by a V1P5S rail, the V1P5S rail sequencing should meet the

same sequencing requirements as the V1P8S rail.

Table 59. S4/S5 to S0 (Power Up) Sequence

Parameter

Min

Max

Unit

RTC_VCC to ILB_RTC_TEST# and ILB_RTC_RTC# de-
assertion
RTC_VCC to PMC_RSMRST# de-assertion

V3P3A (SUS Rails) valid to PMC_RSMRST# de-assertion
(t1 still applies in applications without RTC battery)

PMC_RSMRST# to Internal RTC Clock assumed stable

Internal RTC Clock assumed stable to PMC_SUSCLK[0]
toggling

PMC_SLP_S4# de-assertion to PMC_SLP_S3# de-
assertion

t6a

Core well stable to DRAM_CORE_PWROK and
PMC_CORE_PWROK assertion (No PCIe devices)

t6b

Core well stable to DRAM_CORE_PWROK and
PMC_CORE_PWROK assertion (for power rails needed by
PCIe devices)

DRAM/PMC_CORE_PWROK to PMC_SUS_STAT#

PMS_SUS_STAT# de-assertion to PMC_PLTRST# de-
assertion