Intel E3815 FH8065301567411 Data Sheet

Product codes
FH8065301567411
Page of 5308
Intel
®
 Atom™ Processor E3800 Product Family
1026
Datasheet
28:23
0b
RO
SOURCE_FOR_PERFORMANCE_COUNTER: 
These bits indicate the source for the 
performance counter. 
000000 = Overlay Register Request Latency [DevBW] and [DevCL] 
000001 = VGA Font Request Latency 
000010 = VGA Character Request Latency 
000011 = Display A FIFO Status 
000100 = Display B FIFO Status 
000101 = Sprite A FIFO Status 
000110 = Cursor A FIFO Status 
000111 = Cursor B FIFO Status 
001000 = Display Steamer A TLB Latency 
001001 = Display Streamer B TLB Latency 
001010 = Sprite Streamer A TLB Latency 
001011 = Cursor Streamer A TLB Latency 
001100 = Cursor Streamer B TLB Latency 
001101 = Overlay Streamer TLB Latency [DevBW] and [DevCL] 
001110 = Display Steamer A Request Latency 
001111 = Display Streamer B Request Latency 
010000 = Sprite Streamer A Request Latency 
010001 = Cursor Streamer A Request Latency 
010010 = Cursor Streamer B Request Latency 
010011 = Overlay Streamer Request Latency [DevBW] and [DevCL] 
010100 = Display A Command Request Latency 
010101 = Display B Command Request Latency 
010110 = Sprite A Command Request Latency 
010111 = Cursor A Command Request Latency 
011000 = Cursor B Command Request Latency 
011001 = Overlay Command Request Latency [DevBW] and [DevCL] 
011010 = DPFC Dummy Read [DevCTG] 
011011 = DPFC Self Refresh [DevCTG] 
011100 = Sprite B FIFO status 
011101 = Sprite C FIFO status 
011110 = Sprite D FIFO status 
011111 = Sprite B TLB Request Latency 
100000 = Sprite C TLB Request Latency 
100001 = Sprite D TLB Request Latency 
100010 = Sprite B Request Latency 
100011 = Sprite C Request Latency 
100100 = Sprite D Request Latency 
100101 = Sprite B Command Request Latency 
100110 = Sprite C Command Request Latency 
101001 = InSR to HP Put (first put after inSR failing edge) 
101000 = SR exit to data HP Put (measure the latency from the SRexit failing edge to 
the first data HP Put. This event shall be measured by either planeB, SpriteC, SpriteD, or 
CurB in pipeB) 
101001 = InSR to data HP Put (measure the latency from any data request made during 
inSR is active to the first data HP Put. This event shall be measured by either planeB, 
SpriteC, SpriteD, or CurB in pipeB) 
101010 = SR exit to TLB HP Put (measure the latency from the SRexit failing edge to 
the first TLB HP Put. This event shall be measured by either planeB, SpriteC, SpriteD, or 
CurB in pipeB ) 
101011 = InSR to TLB HP Put (measure the latency from any TLB request made during 
inSR is active to the first TLB HP Put. This event shall be measured by either planeB, 
SpriteC, SpriteD, or CurB in pipeB )
22:16
0b
RO
RESERVED: 
Write as zero.
15:0
0b
RO
PERFORMANCE_COUNTER_VALUE: 
This is the value of the performance counter for 
the source indicated in the source field.
Bit 
Range
Default & 
Access
Field Name (ID): Description