Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
Datasheet
1027
14.12
Memory Mapped Registers (Read Only)
14.12.1
ST01 (ST01_MDA)—Offset 3BAh
Input Status 1
Access Method
Default: 00h
Table 172.
Summary of Display Memory Mapped I/O Registers—GTTMMADR_LSB
Offset
Size
(Bytes)
Register Name (Register Symbol)
Default
Value
3BA–3BAh
1
00h
3C2–3C2h
1
00h
3C7–3C7h
1
00h
3DA–3DAh
1
00h
Type:
Memory Mapped I/O Register
(Size: 8 bits)
Offset:
GTTMMADR_LSB Type:
PCI Configuration Register (Size: 32
bits)
GTTMMADR_LSB Reference:
GTTMMADR_LSB Reference:
[B:0, D:2, F:0] + 10h
7
4
0
0
0
0
0
0
0
0
0
RE
SER
V
ED_A
S
_
PE
R_VG
A_SP
EC
IFIC
A
T
ION
RE
SERV
ED
VID
E
O_FE
EDBAC
K
_1
_0
VER_TI_CAL_RE
T
RACE_VID
EO
RE
SE
RVED_1
DIS_PLA
Y
_E
NA_BLE_OU
T
P
U
T
Bit
Range
Default &
Access
Field Name (ID): Description
7
0b
RO
RESERVED_AS_PER_VGA_SPECIFICATION:
Read as 0s.
6
0b
RO
RESERVED:
Read as 0.
5:4
0b
RO
VIDEO_FEEDBACK_1_0:
These are diagnostic video bits that are selected by the Color
Plane Enable Register. These bits that are programmably connected to 2 of the 8 color
bits sent to the palette. Bits 4 and 5 of the Color Plane Enable Register (AR12) selects
which two of the 8 possible color bits become connected to these 2 bits of this register.
The current software normally does not use these 2 bits. They exist for EGA
compatibility.