Intel E3815 FH8065301567411 Data Sheet

Product codes
FH8065301567411
Page of 5308
 
Intel
®
 Atom™ Processor E3800 Product Family
Datasheet
1029
14.12.3
DACSTATE—Offset 3C7h
DAC State Register
Access Method
Default: 00h
7
4
0
0
0
0
0
0
0
0
0
CR
T_
IN
TE
R
_
R
U
PT
_
P
EN
D
IN
G
RE
SE
RVED
RGB_COMP
A
R
A
TOR_S
ENSE
RESE
RVED
_1
Bit 
Range
Default & 
Access
Field Name (ID): Description
7
0b
RO
CRT_INTER_RUPT_PENDING: 
This bit is here for EGA compatibility and will always 
return zero. Note that the generation of interrupts was originally enabled, through bits 
[4,5] of the Vertical Retrace End Register (CR11). This ability to generate interrupts at 
the start of the vertical retrace interval is a feature that is typically unused by DOS 
software and therefore is only supported through other means for use under a operating 
system support.  
0 = CRT (vertical retrace interval) interrupt is not pending.  
1 = CRT (vertical retrace interval) interrupt is pending
6:5
0b
RO
RESERVED: 
Read as 0s.
4
0b
RO
RGB_COMPARATOR_SENSE: 
This bit returns the state of the output of the RGB 
output comparator(s). Video BIOS uses this bit during POST to determine whether the 
display is connected and if it is a color or monochrome CRT. BIOS blanks the screen or 
clears the frame buffer to display only black. Next, BIOS outputs a ramp to the D-to-A 
converters to test for the presence of a color display by determining which code cause 
the comparator to switch. Finally, if the BIOS does not detect any termination resistors 
on Red or Blue, it tests for the presence of a display using the Green signal. The result 
of each such test is read via this bit. 
0 = Below threshold 
1 = Above threshold
3:0
0b
RO
RESERVED_1: 
Read as 0s.
Type: 
Memory Mapped I/O Register
(Size: 8 bits)
Offset: 
GTTMMADR_LSB Type: 
PCI Configuration Register (Size: 32 
bits)
GTTMMADR_LSB Reference: 
[B:0, D:2, F:0] + 10h
7
4
0
0
0
0
0
0
0
0
0
RES
E
RV
ED
D
A
C_S
TA
T
E