Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
1030
Datasheet
14.12.4
ST01 (ST01_CGA)—Offset 3DAh
Input Status 1
Access Method
Default: 00h
Bit
Range
Default &
Access
Field Name (ID): Description
7:2
0b
RO
RESERVED:
Read as 0.
1:0
0b
RO
DAC_STATE:
This field indicates which of the two index registers was most recently
written.
Bits [1:0] Index Register Indicated
00 Palette Write Index Register at I/O Address 3C7h (default)
01 Reserved
10 Reserved
11 Palette Read Index Register at I/O Address 3C8h
Type:
Memory Mapped I/O Register
(Size: 8 bits)
Offset:
GTTMMADR_LSB Type:
PCI Configuration Register (Size: 32
bits)
GTTMMADR_LSB Reference:
GTTMMADR_LSB Reference:
[B:0, D:2, F:0] + 10h
7
4
0
0
0
0
0
0
0
0
0
RE
SERV
ED_A
S
_
PE
R_VG
A_SP
EC
IFIC
A
T
ION
RE
SERV
ED
VID
E
O_FE
EDBAC
K
_1
_0
VER_TI_CAL_RE
T
RACE_VID
EO
RE
SE
RVED_1
DIS_PLA
Y
_E
N
A
_BLE_OU
T
P
U
T
Bit
Range
Default &
Access
Field Name (ID): Description
7
0b
RO
RESERVED_AS_PER_VGA_SPECIFICATION:
Read as 0s.
6
0b
RO
RESERVED:
Read as 0.
5:4
0b
RO
VIDEO_FEEDBACK_1_0:
These are diagnostic video bits that are selected by the Color
Plane Enable Register. These bits that are programmably connected to 2 of the 8 color
bits sent to the palette. Bits 4 and 5 of the Color Plane Enable Register (AR12) selects
which two of the 8 possible color bits become connected to these 2 bits of this register.
The current software normally does not use these 2 bits. They exist for EGA
compatibility.