Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
Datasheet
1033
14.13
Memory Mapped Registers (Write Only)
14.13.1
FCR (FCR_MDA_Write)—Offset 3BAh
Feature Control
Access Method
Default: 00h
14.13.2
MSR (MSR_Write)—Offset 3C2h
Miscellaneous Output
Access Method
Table 173.
Summary of Display Memory Mapped I/O Registers—GTTMMADR_LSB
Offset
Size
(Bytes)
Register Name (Register Symbol)
Default
Value
3BA–3BAh
1
00h
3C2–3C2h
1
00h
3C7–3C7h
1
00h
3DA–3DAh
1
00h
Type:
Memory Mapped I/O Register
(Size: 8 bits)
Offset:
GTTMMADR_LSB Type:
PCI Configuration Register (Size: 32
bits)
GTTMMADR_LSB Reference:
GTTMMADR_LSB Reference:
[B:0, D:2, F:0] + 10h
7
4
0
0
0
0
0
0
0
0
0
RE
SERV
ED
VS
Y
N
C_C
O
NTRO
L
RE
SE
RVED_1
Bit
Range
Default &
Access
Field Name (ID): Description
7:4
0b
RW
RESERVED:
Read as 0.
3
0b
RW
VSYNC_CONTROL:
This bit is provided for compatibility only and has no other
function. Reads and writes to this bit have no effect other than to change the value of
this bit. The previous definition of this bit selected the output on the VSYNC pin.
0 = Was used to set VSYNC out put on the VSYNC pin (default).
1 = Was used to set the log i cal 'OR' of VSYNC and Display Ena ble output on the
VSYNC pin. This capability was not typically very useful..
2:0
0b
RW
RESERVED_1:
Read as 0.