Intel E3815 FH8065301567411 Data Sheet

Product codes
FH8065301567411
Page of 5308
 
Power Up and Reset Sequence
Intel
®
 Atom™ Processor E3800 Product Family
Datasheet
105
Note:
1. It is not possible to wake the SoC using this event after a Global Reset, Go-to-S5 
type reset.
2. When the HDA_LPE_V1P5V1P8_S3 is powered by a V1P5S rail, the V1P5S rail 
sequencing should meet the same sequencing requirements as the V1P8S rail.
7.3.3
Handling Power Failures
The power failures can occur if the AC power or battery is removed. In this case, when 
the system was originally in a S0 state, power failure bit (GEN_PMCON1.PWR_FLR) is 
set after a power failure. Software can clear the bit.
7.4
Reset Behavior
There are several ways to reset the processor.
PMC_WAKE_PCIE[0:3]#
1
(PCI Express WAKE#)
External
PM1_STS_EN.PCIEXP_WAKE_DIS register bit
Note: When the PMC_WAKE_PCIE# pin is active and 
the PM1_STS_EN.PCIEXP_WAKE_DIS register bit is 
clear, CPU will wake the platform.
Primary PME#
1
Internal
GPEOa_EN.PME_B0_EN register bit. This wake status 
bit includes multiple internal agents:
HD Audio
EHCI (USB2) xHCI
SATA
Note: SATA can only trigger a wake event if it had 
asserted its PME prior to S3/S4/S5 entry and software 
doesn't clear GPE0a_STS.PME_B0_STS, a wake event 
would still result.
PME_B0_S5_DIS bit is used to prevent these devices 
from waking from S5. Does not apply to wake from S3.
PMC - Initiated
1
Internal
No enable bits. The PMC can wake the host 
independent of other wake events listed, if desired. A 
bit is provided in PRSTS for reporting this wake event 
to BIOS. Note that this wake event may be used as a 
wake trigger on behalf of some other wake source.
Table 60. S3/S4/S5 to S0 Cause of Wake Events (Sheet 2 of 2)
Cause
Type
How Enabled