Intel E3815 FH8065301567411 Data Sheet

Intel

®

 Atom™ Processor E3800 Product Family

1052

Datasheet

Revision Identification and Class Codes

Default: 04800001h

31:21

0h

RO

Reserved

20

1b

RO

CAPABILITY_LIST: Indicates that the CAPPOINT register at 34h provides an offset 

into PCI Configuration Space containing a pointer to the location of the first item in the 

list.

19

0b

RO

INTERRUPT_STATUS: Reflects the state of the interrupt in the camera device. Is set 

to 1 if IER and IIR are both set. Otherwise is set to 0.

18:11

0h

RO

Reserved

10

0b

RW

INTERRUPT_DISABLE: When 1, blocks the sending of ASSERT_INTA and 

DEASSERT_INTA messages to the Intel Legacy Block (ILB). The interrupt status is not 

blocked from being reflected in PCICMDSTS.IS. When 0, permits the sending of 

ASSERT_INTA and DEASSERT_INTA messages to the ILB.

9:3

0h

RO

Reserved

2

0h

RW

BUS_MASTER_ENABLE: Enables ISP to function as a PCI compliant master. When 

0, blocks the sending of MSI interrupts. When 1, permits the sending of MSI interrupts.

1

0h

RW

MEMORY_SPACE_ENABLE: When set, accesses to this device's memory space is 

enabled. When 1, the ISP will compare the incoming address on the IOSF bus with 

ISPMMADR(31:22). If there is a match and if the IOSF command is either a MEMRD or 

MEMWR, the ISP will select the command and present it on the AHB bus. When 0, the 

ISP will not claim MEMRD or MEMWR IOSF commands.

0

0h

RO

Reserved

PCI Configuration Register

(Size: 32 bits)

31

28

24

20

16

12

8

4

0

0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1

BCC

SC

C

PI

RID

31:24

04h

RO

BASE_CLASS_CODE: Indicates a multimedia device.

23:16

80h

RO

SUB_CLASS_CODE: Indicates other multimedia device.

15:8

0h

RO

PROGRAMMING_INTERFACE: Default programming interface.

7:0

01h

RO

REVISION_ID: The value in this field reflects the value of strapRID(7:0) (which is 

an input pin of ISP) and can be changed with each stepping of the silicon.