Intel E3815 FH8065301567411 Data Sheet

 

Intel

®

 Atom™ Processor E3800 Product Family

Datasheet

1059

Performance

Default: 00000000h

24

0h

RW

IER: This is an enable bit that allows the sending of an interrupt to the CPU using 

either MSI or INTR mechanisms. The interrupt is sent immediately to the CPU. The 

firmware running on the ISP guarantees ordering by reading the last data write from 

memory before raising the interrupt. 1 = If MSI_ENABLE is set, then an MSI is sent to 

the CPU when the IIR bit is set, or if the IIR bit remains set after software writes to this 

register. If INTERRUPT_DISABLE is not set, then an ASSERT_INTA message is sent to 

the Intel Legacy Block (ILB) when the IIR bit is set by hardware, or if the IIR bit remains 

set after software writes to this register. If software clears the IIR bit, and 

INTERRUPT_DISABLE is not set then a DEASSERT_INTA message is sent to the ILB. 0 = 

Do not generate an MSI even if the MSI_ENABLE bit is set. Do not send ASSERT_INTA or 

DEASSERT_INTA messages to the ILB even if the INTERRUPT_DISABLE bit is not set.

23:17

0h

RO

Reserved

16

0h

RW/1C

IIR: This is the persistent value of the interrupt bit. It is set by hardware, and 

cleared by software. Software must write a 1 to clear this bit. Writing a 0 is a NOP. If 

both software and hardware attempt to write to this field in the same clock cycle, 

hardware wins. 1 = An interrupt was received from the vendor IP when the IMR bit was 

not set, and software has not yet cleared it. 0 = There is no pending interrupt.

15:9

0h

RO

Reserved

8

1b

RW

IMR: Interrupt Mask bit. 1 = IIR bit will not be set when the ISR bit is set. 0 = IIR 

bit will be set when the ISR bit is set.

7:1

0h

RO

Reserved

0

0h

RO

ISR: Reflects the state of the interrupt line from the vendor IP, after it is 

synchronized to the czclk domain.

PCI Configuration Register

(Size: 32 bits)

31

28

24

20

16

12

8

4

0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

CR

IF

LO

31:0

0h

RW/SE

IUNIT has four performance counters. When counting is enabled, the 11-bit 

reads_in_flight counter keeps track of the number of outstanding reads that have been 

requested, but not yet returned back at the OCP master interface. The 11-bit 

max_reads_in_flight counter keeps track of the maximum number of reads in flight in 

any given clock cycle. Each clock cycle, if there are any reads in flight, the 

reads_in_fight counter is added to a 64-bit cumulative_reads_in_flight counter, and the 

48-bit active_cycles counter is incremented by 1. Reading this register returns bits 31:0 

of the cumulative_reads_in_flight counter. This counter should be read only after 

counting is disabled. Reading while the counters are enabled will return undefined 

values. All four counters are disabled at reset. Writing (any value) to this register, will 

enable all four counters.