Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
1060
Datasheet
15.7.16
iunit_PERF1_type (PERF1)—Offset B4h
Performance
Access Method
Default: 00000000h
15.7.17
iunit_PERF2_type (PERF2)—Offset B8h
Performance
Access Method
Default: 00000000h
Type:
PCI Configuration Register
(Size: 32 bits)
PERF1:
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
CRIFHI
Bit
Range
Default &
Access
Description
31:0
0h
RW/SE
CRIFHI:
IUNIT has four performance counters. When counting is enabled, the 11-bit
reads_in_flight counter keeps track of the number of outstanding reads that have been
requested, but not yet returned back at the OCP master interface. The 11-bit
max_reads_in_flight counter keeps track of the maximum number of reads in flight in
any given clock cycle. Each clock cycle, if there are any reads in flight, the
reads_in_fight counter is added to a 64-bit cumulative_reads_in_flight counter, and the
48-bit active_cycles counter is incremented by 1. Reading this register returns bits
63:32 of the cumulative_reads_in_flight counter. This counter should be read only after
counting is disabled. Reading while the counters are enabled will return undefined
values. All four counters are disabled at reset. Writing (any value) to this register, will
disable all four counters.
Type:
PCI Configuration Register
(Size: 32 bits)
PERF2:
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
AC
LO
Bit
Range
Default &
Access
Description
31:0
0h
RW/SE
ACLO:
IUNIT has four performance counters. When counting is enabled, the 11-bit
reads_in_flight counter keeps track of the number of outstanding reads that have been
requested, but not yet returned back at the OCP master interface. The 11-bit
max_reads_in_flight counter keeps track of the maximum number of reads in flight in
any given clock cycle. Each clock cycle, if there are any reads in flight, the
reads_in_fight counter is added to a 64-bit cumulative_reads_in_flight counter, and the
48-bit active_cycles counter is incremented by 1. Reading this register returns bits 31:0
of the active_cycles counter. This counter should be read only after counting is disabled.
Reading while the counters are enabled will return undefined values. All four counters
are disabled at reset. Writing (any value) to this register, will clear all four counters. The
counters should only be cleared after they are disabled.