Intel E3815 FH8065301567411 Data Sheet

 

Intel

®

 Atom™ Processor E3800 Product Family

Datasheet

1061

Performance

Default: 00000000h

OCP Master Write Data

Default: FFFFFFFFh

PCI Configuration Register

(Size: 32 bits)

31

28

24

20

16

12

8

4

0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RSVD_31_27

MRIF

AC

H

I

31:27

0h

RO

Reserved

26:16

0h

RW/SE

IUNIT has four performance counters. When counting is enabled, the 11-bit 

reads_in_flight counter keeps track of the number of outstanding reads that have been 

requested, but not yet returned back at the OCP master interface. The 11-bit 

max_reads_in_flight counter keeps track of the maximum number of reads in flight in 

any given clock cycle. Each clock cycle, if there are any reads in flight, the 

reads_in_fight counter is added to a 64-bit cumulative_reads_in_flight counter, and the 

48-bit active_cycles counter is incremented by 1. Reading this register returns bits 11:0 

of the max_reads_in_flight counter. This counter should be read only after counting is 

disabled. Reading while the counters are enabled will return undefined values. All four 

counters are disabled at reset. Writing (any value) to this register, will clear the 

max_reads_in_flight counters only. The counters should only be cleared after they are 

disabled.

15:0

0h

RW/SE

IUNIT has four performance counters. When counting is enabled, the 11-bit 

reads_in_flight counter keeps track of the number of outstanding reads that have been 

requested, but not yet returned back at the OCP master interface. The 11-bit 

max_reads_in_flight counter keeps track of the maximum number of reads in flight in 

any given clock cycle. Each clock cycle, if there are any reads in flight, the 

reads_in_fight counter is added to a 64-bit cumulative_reads_in_flight counter, and the 

48-bit active_cycles counter is incremented by 1. Reading this register returns bits 

47:32 of the active_cycles counter. This counter should be read only after counting is 

disabled. Reading while the counters are enabled will return undefined values. All four 

counters are disabled at reset. Writing (any value) to this register, will clear the 

max_reads_in_flight counters only. The counters should only be cleared after they are 

disabled.

PCI Configuration Register

(Size: 32 bits)