Intel E3815 FH8065301567411 Data Sheet

Intel

®

 Atom™ Processor E3800 Product Family

1066

Datasheet

AFE RCOMP control

Default: 00000000h

31:24

64h

RW

HS_CLK_UNGATE_DLY: Delay between the assertion of HS 

enable and the ungating of the HS clocks going to the DPHY logic for all clock lanes. HS 

clocks are gated by default and are ungated after Tclk-settle time. The range of this field 

is 0 nsec to 510 nsec in increments of 2 nsec, with reset value 0x64 indicating 200 nsec. 

Note that we use czclk to increment the counter, hence the actual delay can be as much 

as 10 nsec larger than the programmed value.

23:22

0h

RW

Reserved

21:20

00b

RW

CSI3_CLK_HS_TERM_OVRD: Override for HS 

termination enable for CSI3 clock lane. 00b = Use the termination enable output from 

the DPHY IP and gate XOR clocks in high speed mode; 01b = Keep HS termination (and 

HS enable) always on; 10b = Generate HS termination by sampling the CP/CN lines 

using coreclk and gate XOR clocks in high speed mode; 11b = Use the termination 

enable output from the DPHY IP;

19:18

00b

RW

CSI2_CLK_HS_TERM_OVRD: Override for HS 

termination enable for CSI2 clock lane. 00b = Use the termination enable output from 

the DPHY IP and gate XOR clocks in high speed mode; 01b = Keep HS termination (and 

HS enable) always on; 10b = Generate HS termination by sampling the CP/CN lines 

using coreclk and gate XOR clocks in high speed mode; 11b = Use the termination 

enable output from the DPHY IP;

17:16

00b

RW

CSI1_CLK_HS_TERM_OVRD: Override for HS 

termination enable for CSI1 clock lane. 00b = Use the termination enable output from 

the DPHY IP and gate XOR clocks in high speed mode; 01b = Keep HS termination (and 

HS enable) always on; 10b = Generate HS termination by sampling the CP/CN lines 

using coreclk and gate XOR clocks in high speed mode; 11b = Use the termination 

enable output from the DPHY IP;

15:8

0Ah

RW

HS_CLK_EN_DLY: Delay between the assertion of HS termination 

enable and the assertion of HS enable for all clock lanes. The range of this field is 0 nsec 

to 510 nsec in increments of 2 nsec, with reset value 0x0A indicating 20 nsec. Note that 

we use czclk to increment the counter, hence the actual delay can be as much as 10 

nsec larger than the programmed value.

7:0

0h

RW

HS_DATA_EN_DLY: Delay between the assertion of HS 

termination enable and the assertion of HS enable for all data lanes. The range of this 

field is 0 nsec to 510 nsec in increments of 2 nsec, with reset value 0x0 indicating 0 

nsec. Note that we use czclk to increment the counter, hence the actual delay can be as 

much as 10 nsec larger than the programmed value.

PCI Configuration Register

(Size: 32 bits)