Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
Datasheet
1067
15.7.28
iunit_IUNIT_AFE_TRIM_CONTROL_type
(IUNIT_AFE_TRIM_CONTROL)—Offset E4h
Configurable delay for CSI AFE data/clk lanes
Access Method
Default: 00000000h
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RSVD_31_16
RSVD_15_9
IC
SI_RC
O
M
PST
A
T
ICLEGDIS
RSVD_7_4
ICSI_RCOMPT
A
RGET
Bit
Range
Default &
Access
Description
31:16
0h
RO
RSVD_31_16:
Reserved
15:9
0h
RW
RSVD_15_9:
Reserved
8
0b
RW
ICSI_RCOMPSTATICLEGDIS:
ICSI_RCOMPSTATICLEGDIS: Disable RCOMP static leg
in AFE
7:4
0h
RW
RSVD_7_4:
Reserved
3:0
0h
RW
ICSI_RCOMPTARGET:
ICSI_RCOMPTARGET: RCOMP target level range is 70ohm to
130ohm differential impedance. 0000b = 50ohms; 0001b = 30ohms; 0010b = 35ohms;
0011b = 40ohms; 0100b = 45ohms; 0101b = 55ohms; 0110b = 60ohms; 0111b =
65ohms;
Type:
PCI Configuration Register
(Size: 32 bits)
IUNIT_AFE_TRIM_CONTROL:
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
IC
SI3_H
SRX
C
LKTRIM
IC
SI2_H
SRX
C
LKTRIM
IC
SI2_H
SRXD
A
TA
T
RIM
IC
SI1_H
SRX
C
LKTRIM
IC
SI1_H
SRXD
A
TA
T
RIM
Bit
Range
Default &
Access
Description
31:28
0h
RW
ICSI3_HSRXCLKTRIM:
ICSI3_HSRXCLKTRIM: Delay for CSI3 clock lane. Refer to the
CSI AFE Circuit Architecture Spec (CAS) for the actual delays for each trim value setting.