Intel E3815 FH8065301567411 Data Sheet

 

Intel

®

 Atom™ Processor E3800 Product Family

Datasheet

1069

IUNIT Deadline Control Register

Default: 040A0100h

1

0b

RW

1 = Disable MIPI CSI2 interface. 0 = Enable MIPI CSI2 interface if 

FB_csi_portdisable[1] fuse is cleared

0

0b

RW

1 = Disable MIPI CSI1 interface. 0 = Enable MIPI CSI1 interface if 

FB_csi_portdisable[0] fuse is cleared

PCI Configuration Register

(Size: 32 bits)

31

28

24

20

16

12

8

4

0

0 0 0 0 0 1 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0

FDD

DI

RSVD_15_12

MDD

RSVD_7_4

IGNORE_W

AKEUP

DIS_G

T

P

64_CHK

DS

31:24

04h

RW

FIRST_DEADLINE_DELAY: Delay between the rising edge of WAKEUP signal and 

the fake deadline that will be specified for the first request of that line. Unit in 250 nsec. 

Reset value of 8'h04 indicates FDD = 1 usec.

23:16

0Ah

RW

DEADLINE_INCREMENT: Difference in deadline times between adjacent requests. If 

the current request is for 32B, the next deadline will be DI more than the current 

deadline. If the current request is for 64B, the next deadline will be 2*DI more than the 

current deadline. Unit in 1/1024 usec. Reset value of 8'h0A indicates DI = 9.765625 

nsec.

15:12

0h

RW

Reserved

11:8

1h

RW

MINIMUM_DEADLINE_DELAY: Minimum separation between current Global Timer 

value and the deadline specified with any request on the PFI interface. Unit is 250 nsec. 

Reset value of 4'h1 indicates MDD = 250 nsec.

7:4

0h

RW

Reserved

3

0b

RW

If clear, then after each rising edge of sdram_wakeup, the OCP 

master interface is stalled until all reads in flight and all FIFOs are empty and then the 

next deadline is set to GT + FDD. If set, the sdram_wakeup signal from ISP_CSS is 

ignored.

2

0b

RW

If clear, then the PFI interface is stalled whenever the next deadline 

value exceeds GT + 64 usec. This check is a safety measure to make sure that deadline 

does not drift too far into the future. If set, this check is not performed.