Intel E3815 FH8065301567411 Data Sheet

Product codes
FH8065301567411
Page of 5308
 
Intel
®
 Atom™ Processor E3800 Product Family
Datasheet
1073
15.7.34
iunit_IUNIT_CONTROL_type (IUNIT_CONTROL)—Offset FCh
IUNIT Control Register
Access Method
Default: 00000103h
7
0b
RO
RSVD_7_7: 
Reserved
6:4
0h
RO
TCGSM: 
ISP trunk clock gating state machine. 0h = RUN_TRUNK_CLK; 1h = 
STOP_TRUNK_CLK; 2h = WAIT_FOR_RESUME; 3h = START_TRUNK_CLK; 4h = 
WAIT_FOR_LOCAL_CLK_TO_START. The reset value will be RUN_TRUNK_CLK. If the 
FB_override_initial_clock_gating fuse is not set, then shortly after reset, the value of 
this register will automatically change to STOP_TRUNK_CLK.
3
0b
RO
RSVD_3_3: 
Reserved
2:1
0h
RO
LCGSM: 
ISP local clock gating state machine. 0h = RUN_LOCAL_CLK; 1h = 
WAIT_FOR_FIFO_EMPTY; 2h = STOP_LOCAL_CLK. The reset value will be 
RUN_LOCAL_CLK. If the FB_override_initial_clock_gating fuse is not set, then shortly 
after reset, the value of this register will automatically change to STOP_LOCAL_CLK.
0
1b
RO
ISP_BUSY: 
ISP_BUSY: 1 = ISP is busy; 0 = ISP is idle.
Bit 
Range
Default & 
Access
Description
Type: 
PCI Configuration Register
(Size: 32 bits)
IUNIT_CONTROL: 
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 1
FUN
T
ION_DIS
A
B
LE_CFG
FU
NCTION_DIS
ABLE
_MM
IO
RSVD_29_29
PE
RF_MAS
K
RSVD_23_22
DIS
A
BLE_ISM_IDLE_FREEZE
DIS
A
BLE
_
OC
P_P
H
AS
E_ORD
E
RING
ICACHE_CMD_WEIGHT
TH
ER
M
_
M
A
S
K
MI
D
RCOMP
C
LK
_
G
A
T
IN
G_DIS
A
BLE
ISP
C
LK_
G
A
T
IN
G_DIS
A
BLE
DD
M
A
SRSE
IBEWC
IB
ERC
Bit 
Range
Default & 
Access
Description
31
0b
RW
FUNTION_DISABLE_CFG: 
FUNCTION_DISABLE_CFG: When set, the IUNIT stops 
accepting any new Configuration cycle requests on the IOSF Primary bus including any 
new configuration cycle requests to clear this bit. Both legacy and MSI interrupts are 
disabled as well.
30
0b
RW
FUNCTION_DISABLE_MMIO: 
FUNCTION_DISABLE_MMIO: When set, the IUNIT stops 
accepting any new MMIO access requests on the IOSF Primary bus.
29
0b
RW
RSVD_29_29: 
Reserved