Intel E3815 FH8065301567411 Data Sheet

Intel

®

 Atom™ Processor E3800 Product Family

1074

Datasheet

28:24

0h

RW

PERF_MASK: This field determines the amount of performance throttling 

applied to ispclk. The value of this field determines how many beat periods of ispclk are 

killed, where a beat period is defined as 16 ispclk cycles. A 16 cycle period was chosen 

to make the throttling independent of the actual clock ratio between ispclk and coreclk. 

Note that clock gating should be enabled when thermal throttling is enabled.

23:22

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RW

Reserved

21

0h

RW

DISABLE_ISM_IDLE_FREEZE: When IUNIT receive a 

RESET_WARN message from PUNIT, it will freeze the IOSF primary Idle State Machine 

(among other things), before sending an OK_TO_RESET message to PUNIT. If the 

DISABLE_ISM_IDLE_FREEZE bit is set, IUNIT will not freeze the ISM in the IDLE state as 

part of this reset sequence.

20

0h

RW

DISABLE_OCP_PHASE_ORDERING: By default, 

IUNIT will follow the OCP phase ordering protocol and wait until a write command is 

accepted before accepting the write data corresponding to that command. If the 

DISABLE_OCP_PHASE_ORDERING bit is set, the IUNIT wrapper will accept the write 

data independent of the write command.

19

0h

RW

ICACHE_CMD_WEIGHT: 0b = Requests from the OCP master 

port sending Icache miss traffic will win arbitration over requests from the OCP master 

port that sends pixel data traffic. 1b = Requests from the two OCP master interfaces will 

be accepted in a round robin fashion.

18:16

0h

RW

THERM_MASK: This field determines the amount of thermal throttling 

applied to ispclk. The value of this field determines how many beat periods of ispclk are 

killed, where a beat period is defined as 16 ispclk cycles. A 16 cycle period was chosen 

to make the throttling independent of the actual clock ratio between ispclk and coreclk. 

000 = No throttling; 001 = 12.5% throttling; 010 = 25% throttling; 011 = 37.5% 

throttling; 100 = 50% throttling; 101 = 62.5% throttling; 110 = 75% throttling; 111 = 

87.5% throttling;

15:8

01h

RW

MIN_IDLE_DELAY: Minimum wait time after the rising edge of idle, before the 

clock gating state machine will start the sequence to gate ispclk. Range is 0 to 130 usec. 

Unit is 0.512 usec. Reset value of 8'h1 indicates MID = 0.512 usec.

7

0b

RW

1 = Disable clock gating for rcompclk. 0 = Enable 

clock gating for rcompclk. Note: All clock gating is disabled by hardware while reset is 

asserted, regardless of the state of this field.

6:5

00b

RW

ISPCLK_GATING_DISABLE: 11 = Disable local clock 

gating and trunk clock gating for ispclk.; 10 = Enable local clock gating for ispclk, but 

disable trunk clock gating.; 01 = Reserved; 00 = Enable local clock gating and trunk 

clock gating for ispclk. Note: All clock gating is disabled by hardware while reset is 

asserted, regardless of the state of this field.

4

0b

RW

1 = Disable DMA. Stop sending any requests on the IB PFI port. 0 = Enable 

DMA. IB PFI port operates normally.

3:2

0h

RW

SOFT_RESET_SEQUENCE_ENABLE: If SRSE=2b00: When an 

IUNIT_RESET_WARN message is received from PUNIT, IUNIT will a) stop accepting 

requests on the IOSF primary interface, b) stop accepting new requests from the OCP 

master interface, c) wait until read data from all earlier read requests received from the 

OCP master interface have been returned by SSA, d) wait until SSA reads data for all 

earlier PFI write requests, and e) wait for all DPHY lanes to enter stop state (LP11), and 

then f) send an IUNIT_OK_TO_RESET posted message to PUNIT. If SRSE=2b01: When 

an IUNIT_RESET_WARN message is received from PUNIT, IUNIT will a) stop accepting 

requests on the IOSF primary interface, b) stop accepting new requests from the OCP 

master interface, c) wait until read data from all earlier read requests received from the 

OCP master interface have been returned by SSA, d) wait until SSA reads data for all 

earlier PFI write requests, and then e) send an IUNIT_OK_TO_RESET posted message to 

PUNIT. If SRSE=2b10: When an IUNIT_RESET_WARN message is received from PUNIT, 

IUNIT will wait for all DPHY lanes to enter stop state (LP11), and then send an 

IUNIT_OK_TO_RESET posted message to PUNIT. If SRSE=2b11: When an 

IUNIT_RESET_WARN message is received from PUNIT, IUNIT will immediately send an 

IUINT_OK_TO_RESET posted message to PUNIT.