Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
Datasheet
1151
15.8.43
reg_gpd_irq_ctrl_reg_irq_clear_type
(gpd_irq_ctrl_reg_irq_clear)—Offset 50Ch
Access Method
Default: 00000000h
15.8.44
reg_gpd_irq_ctrl_reg_irq_enable_type
(gpd_irq_ctrl_reg_irq_enable)—Offset 510h
Access Method
18
0h
RO
IRQ_STAT_ISP_SMON:
Represents the irq status of the irq_out from the ISP
streaming monitor
17
0h
RO
IRQ_STAT_SP_SMON:
Represents the irq status of the irq_out from the SP streaming
monitor
16
0h
RO
IRQ_STAT_IFMT:
Represents the irq status of the irq_out from the input formatting
subsystem
15
0h
RO
IRQ_STAT_ISEL:
Represents the irq status of the irq_out from the input selector
14
0h
RO
IRQ_STAT_ISYS:
Represents the irq status of the irq_out from the input system
13
0h
RO
IRQ_STAT_ISP:
Represents the irq status of the irq_out from isp2300
12
0h
RO
IRQ_STAT_SP:
Represents the irq status of the irq_out from scalar processor
11:0
0h
RO
IRQ_STAT_GPIO_PINS:
Represents the irq status of the - potentially debounced -
GPIO input pins
Bit
Range
Default &
Access
Description
Type:
Memory Mapped I/O Register
(Size: 32 bits)
gpd_irq_ctrl_reg_irq_clear:
ISPMMADR Type:
PCI Configuration Register (Size: 32 bits)
ISPMMADR Reference:
[B:0, D:3, F:0] + 10h
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
re
g_irq
_
cle
ar
Bit
Range
Default &
Access
Description
31:0
0h
WO
reg_irq_clear:
Clears (set to '0') bits in reg_irq_status. When writing a '1' into a bit of
this register, the corresponding bit in the req_irq_status is cleared. When writing a '0'
into a bit of this register, the corresponding bit in the req_irq_status is not affected.
Type:
Memory Mapped I/O Register
(Size: 32 bits)
gpd_irq_ctrl_reg_irq_enable:
ISPMMADR Type:
PCI Configuration Register (Size: 32 bits)
ISPMMADR Reference:
[B:0, D:3, F:0] + 10h