Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
Datasheet
1153
15.8.47
reg_gpd_gptimer_reg_reset_type (gpd_gptimer_reg_reset)—
Offset 600h
Access Method
Default: 00000000h
15.8.48
reg_gpd_gptimer_overall_enable_type
(gpd_gptimer_overall_enable)—Offset 604h
Access Method
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
re
g_
ir
q
_
st
r_
o
u
t_
en
ab
le
Bit
Range
Default &
Access
Description
31:0
0h
RW
reg_irq_str_out_enable:
Indicates for each bit whether an interrupt cause as
monitored by the req_irq_status register also results in a send token on the irq_str_out
port (value='1') or not (value='0')
Type:
Memory Mapped I/O Register
(Size: 32 bits)
gpd_gptimer_reg_reset:
ISPMMADR Type:
PCI Configuration Register (Size: 32 bits)
ISPMMADR Reference:
[B:0, D:3, F:0] + 10h
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
unu
se
d_re
g_re
se
t
re
g_re
se
t
Bit
Range
Default &
Access
Description
31:8
0h
RW
unused_reg_reset:
Unused
7:0
0h
WO
reg_reset:
GP Timer reset. Write '1' to bit x to reset timer x. Write 0xFF to reset all
timers.
Type:
Memory Mapped I/O Register
(Size: 32 bits)
gpd_gptimer_overall_enable:
ISPMMADR Type:
PCI Configuration Register (Size: 32 bits)
ISPMMADR Reference:
[B:0, D:3, F:0] + 10h