Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
1276
Datasheet
15.8.243 reg_ifmt_irq_ctrl_IFMT_IRQ_ctrl_enable_type
(ifmt_irq_ctrl_IFMT_IRQ_ctrl_enable)—Offset 30A10h
Access Method
Default: 00000000h
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
u
nused_IFMT_IRQ_ctrl_c
le
ar
IFMT_IRQ_ctrl_c
le
ar
Bit
Range
Default &
Access
Description
31:5
0h
RW
unused_IFMT_IRQ_ctrl_clear:
Unused
4:0
0h
WO
IFMT_IRQ_ctrl_clear:
Clears (set to '0') bits in IFMT_IRQ_ctrl_status. When writing a
'1' into a bit of this register, the corresponding bit in the IFMT_IRQ_ctrl_status is
cleared. When writing a '0' into a bit of this register, the corresponding bit in the
IFMT_IRQ_ctrl_status is not affected.
Type:
Memory Mapped I/O Register
(Size: 32 bits)
ifmt_irq_ctrl_IFMT_IRQ_ctrl_enable:
ISPMMADR Type:
PCI Configuration Register (Size: 32 bits)
ISPMMADR Reference:
[B:0, D:3, F:0] + 10h
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
un
use
d
_IFMT_IRQ
_
ct
rl_e
nable
IFMT_IRQ_
ctrl_enable
Bit
Range
Default &
Access
Description
31:5
0h
RW
unused_IFMT_IRQ_ctrl_enable:
Unused
4:0
0h
RW
IFMT_IRQ_ctrl_enable:
Indicates for each bit whether an interrupt cause as
monitored by the IFMT_IRQ_ctrl_status register also affects the IRQ pin (value='1') or
not (value='0')