Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
Datasheet
1277
15.8.244 reg_ifmt_irq_ctrl_IFMT_IRQ_ctrl_edge_pulse_type
(ifmt_irq_ctrl_IFMT_IRQ_ctrl_edge_pulse)—Offset 30A14h
Access Method
Default: 00000000h
15.8.245 reg_isp_dma_DMA_FSM_Command_type
(isp_dma_DMA_FSM_Command)—Offset 40000h
FSM Command: Last command and State
Access Method
Default: 00000001h
Type:
Memory Mapped I/O Register
(Size: 32 bits)
ifmt_irq_ctrl_IFMT_IRQ_ctrl_edge_pulse:
ISPMMADR Type:
PCI Configuration Register (Size: 32 bits)
ISPMMADR Reference:
[B:0, D:3, F:0] + 10h
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
un
used_IFMT_IRQ_c
trl_edge_pu
lse
IFMT_IRQ_c
trl_edge_pu
lse
Bit
Range
Default &
Access
Description
31:5
0h
RW
unused_IFMT_IRQ_ctrl_edge_pulse:
Unused
4:0
0h
RW
IFMT_IRQ_ctrl_edge_pulse:
Indicates for each bit whether an interrupt cause is
translated into a pulse (value='0') or into a constant level '1' (value='1') on the IRQ pin
Type:
Memory Mapped I/O Register
(Size: 32 bits)
isp_dma_DMA_FSM_Command:
ISPMMADR Type:
PCI Configuration Register (Size: 32 bits)
ISPMMADR Reference:
[B:0, D:3, F:0] + 10h
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
E
rro
r_state
RSV
D
0
Er
ror_flag
Stall__flag
R
un_flag
Idle
_flag