Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Electrical Specifications
Intel
®
Atom™ Processor E3800 Product Family
148
Datasheet
9.6.2
Generic Clock Jitter AC Specification
Applies to the following clocks unless overridden below: SIO_I2C[0:6]_CLK,
PMC+PLT_CLK[0:6], SIO_SPI_CLK, LPE_I2S[0:2]_CLK, TAP_CLK, PCU_SPI_CLK,
ILB_LPC_CLK[0:1], SD3_CLK, SD2_CLK, MMC1_CLK, HDA_CLK, SVID_CLK,
DDI[0:1]_DDCCLK, VGA_DDCLK.
PMC+PLT_CLK[0:6], SIO_SPI_CLK, LPE_I2S[0:2]_CLK, TAP_CLK, PCU_SPI_CLK,
ILB_LPC_CLK[0:1], SD3_CLK, SD2_CLK, MMC1_CLK, HDA_CLK, SVID_CLK,
DDI[0:1]_DDCCLK, VGA_DDCLK.
NOTES:
1.
Edge Rate is measured from 10%-90% of supply voltage.
2.
Cycle to cycle jitter measure for 100K samples.
3.
Based on trace length of 25–200 mm, total maximum far end capacitance of 5
pF, EDS of 10 pF and
board impedance
of 30–75 Ω.
4.
Period jitter value is measured by adjusting an oscilloscope to display a little more than one complete
clock cycle with the display set to infinite persistence. Scope trigger is set on the first edge, and the
period jitter is captured by measuring spread/peak-peak value of the second edge. 100K samples.
5.
The TIE is estimated by measuring how far each active edge of the clock varies from its ideal position.
100K samples.
Figure 19.
Crystal Clock Timing
Table 107. Generic Clock Jitter AC Specification
Symbol
Parameter
Min.
Typ
Max.
Unit
Notes
T
RISE
/
FALL
Minimum and Maximum Rise/Fall
Time
Time
1.5
20
ns
1, 3
T
DC
Duty Cycle
45
55
%
2
T
PEAKJIT
Peak Jitter (cycle to cycle)
300
ps
2
T
PERJIT
Period Jitter (peak to peak)
500
ps
4
T
TIE
Time Interval Error (peak to peak)
400
ps
5
T
LONG
Long Term Accuracy
-100
100
ps