Intel E3815 FH8065301567411 Data Sheet

Product codes
FH8065301567411
Page of 5308
 
Electrical Specifications
Intel
®
 Atom™ Processor E3800 Product Family
Datasheet
151
T
CTL
(tCTLVB + tCTLVA)
Total Control buffer Window available 
for Control buffers (CS#, CKE)
1400
ps
2
System Memory Data and Strobe Signal Timings
T
DVB
+T
VDA
Data, DQ and DM timing window 
available at the interface output for 
write commands. tDVB is data 
available before strobe and tDVA is 
data available after corresponding 
slope.
645
ps
3
T
SU 
+ T
HD
Data, DQ Input Setup Plus Hold Time 
requirement for successful Read 
operation. These Setup and Hold 
numbers are measured w.r.t. 
corresponding strobe or Falling Edge
310
ps
4
T
DQSS
Strobe to rising clock edge during 
write.
-120
120
ps
T
WPRE
DQSP/N Preamble duration (one 
dummy cycle)
0.9
tCKAV
G
T
WPST
DQSP/N Postamble Duration
0.4
tCKAV
G
DDR3L Electrical Characteristic and AC timings at 1333 MT/s. DRAM_VDD_S4 = 1.35 V
T
SLR_D
DQ, DQSP, DQSN Input Slew Rate
3
5.5
V/ns
System Memory Clock Timings
T
CK(AVG)
Average CK Period
1.5
ns
T
CH
Average CK High Time
0.45
tCKAV
G
T
CL
Average CK Low Time
0.45
tCKAV
G
T
SKEW
Skew between any System Memory 
Differential Clock Pair (CKP/CKN)
30
ps
System Memory Command Signal Timings
T
CMD
(tCMDVB+tCMDVA)
Total CMD Buffer window available for 
command buffers (RAS#, CAS#, 
WE#, BS[2:0], MA)
1075
ps
1
System Memory Control Signal Timings
T
CTL
(tCTLVB + tCTLVA)
Total Control buffer Window available 
for Control buffers (CS#, CKE)
1125
ps
2
System Memory Data and Strobe Signal Timings
Table 110. DDR3L Interface Timing Specification  (Sheet 2 of 3)
Symbol
Parameter
Min
Max
Unit
Figure
Notes