Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
1568
Datasheet
15.8.662 reg_inp_sys_csi_receiver_csi2_int_enable_type
(inp_sys_csi_receiver_csi2_int_enable)—Offset 80208h
Interrupt Enable
Access Method
Default: 00000000h
9
0h
RW/1C
no_ecc_err:
Set if no ECC error detected in packet
8
0h
RW/1C
err_ecc_corr:
Set if ECC error detected and corrected for one bit
7
0h
RW/1C
err_ecc_double:
Set if ECC error detected for two or more bits
6
0h
RW/1C
err_control:
Set if DPHY flags a control error
5
0h
RW/1C
err_sot_sync_hs:
Set if DPHY flags start of transmission synchronisation error
4
0h
RW/1C
err_sot_hs:
Set if DPHY flags start of transmission error
3
0h
RW/1C
sleep_mode_exit:
Set if DPHY exits ultra low power state
2
0h
RW/1C
sleep_mode_entry:
Set if DPHY enters ultra low power state
1
0h
RW/1C
err_init_timeout:
Set if Initialization timeout error occurs on DPHY data lanes
0
0h
RO
reserved_10:
Always set to 0
Bit
Range
Default &
Access
Description
Type:
Memory Mapped I/O Register
(Size: 32 bits)
inp_sys_csi_receiver_csi2_int_enable:
ISPMMADR Type:
PCI Configuration Register (Size: 32 bits)
ISPMMADR Reference:
[B:0, D:3, F:0] + 10h
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
unus
ed
_csi2_int
_
enab
le
er
r_
line_
sy
nc
err_e
scap
e
er
r_data_ti
m
eout
err_fr
am
e_
data
err_fr
ame
_
sy
nc
er
r_
id
err
_
crc
no_e
cc_e
rr
err_e
cc_c
o
rr
err_e
cc_d
oub
le
er
r_con
trol
err_s
o
t_syn
c_hs
err_s
o
t_hs
sle
ep
_
m
ode
_exit
sl
ee
p
_
m
o
de
_
en
tr
y
er
r_init_ti
m
eout
ove
rr
u
n
Bit
Range
Default &
Access
Description
31:17
0h
RW
unused_csi2_int_enable:
Unused