Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
1582
Datasheet
15.8.679 reg_inp_sys_csi_receiver_csi_sh_be_comp_reg_vc0_type
(inp_sys_csi_receiver_csi_sh_be_comp_reg_vc0)—Offset
8080Ch
Compression scheme register for virtual channel 0
Access Method
Default: 00000000h
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
un
used_c
si_sh_be
_two_ppc
hig
h
_pr
eci
sion
us
e_bo
th_p
orts
Bit
Range
Default &
Access
Description
31:2
0h
RW
unused_csi_sh_be_two_ppc:
Unused
1
0h
RW
high_precision:
When '1', (and use_both_ports='1' as well) both ports A and B are
used to output one high precision pixel, when '0', high_precision pixels are saturated to
fit on one port.
0
0h
RW
use_both_ports:
When '1', both ports A and B are active. When '0' only port A is
active
Type:
Memory Mapped I/O Register
(Size: 32 bits)
inp_sys_csi_receiver_csi_sh_be_comp_reg_vc0:
ISPMMADR Type:
PCI Configuration Register (Size: 32 bits)
ISPMMADR Reference:
[B:0, D:3, F:0] + 10h
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
pr
ed
_u
sd
_t
yp
e8
comp
_
u
sd
_
typ
e8
pr
ed
_u
sd
_t
yp
e7
comp
_
u
sd
_
typ
e7
pr
ed
_u
sd
_t
yp
e6
comp
_
u
sd
_
typ
e6
pr
ed
_u
sd
_t
yp
e5
comp
_
u
sd
_
typ
e5
pr
ed
_u
sd
_t
yp
e4
comp
_
u
sd
_
typ
e4
pr
ed
_u
sd
_t
yp
e3
comp
_
u
sd
_
typ
e3
pr
ed
_u
sd
_t
yp
e2
comp
_
u
sd
_
typ
e2
pr
ed
_u
sd
_t
yp
e1
comp
_
u
sd
_
typ
e1
Bit
Range
Default &
Access
Description
31
0h
RW
pred_usd_type8:
prediction algorithm for vc=0, user defined type 8 data: 0 -) pred1,
1 -) pred2
30:28
0h
RW
comp_usd_type8:
compression format for vc=0, user defined type 8 data: value
between 0 to 6. 0-no compression