Intel E3815 FH8065301567411 Data Sheet

 

Intel

®

 Atom™ Processor E3800 Product Family

Datasheet

159

1.

Measured at each R,G,B termination according to the VESA Test Procedure - Evaluation of Analog Display Graphics 

Subsystems Proposal (Version 1, Draft 4, December 1, 2000).

2.

R,G,B Max Video Rise/Fall Time: 50% of minimum pixel clock period

3.

R,G,B Min Video Rise./Fall Time: 10% of minimum pixel clock period

4.

Max settling time: 30% of minimum pixel clock period

5.

Video channel-to-channel output skew: 25% of minimum pixel clock period

6.

Overshoot/Undershoot: ±12% of “black”-to-”white” video step function

7.

Noise Injection Ratio: 2.5% of maximum luminance voltage (dc to max pixel clock frequency)

8.

R,G,B AC parameters are strongly dependent on the board design & implementation: actual performance may differ from 

values noted above depending on board implementation.

1.

No signal non-monotonicity / excursions allowed in the 0.5 to 2.4V range

2.

Measured over 100,000 intervals. Horizontal refresh rate at all image format, worse-case screen 

patterns. 

Noise Injection 
Ratio

2.5

%

T

RISE

R,G,B Video Rise 
TIme

0.286

1.43

ns

1,2,8 (10-90% of “black”-to-
”white” video transition)

T

FALL

R,G,B Video Fall 
TIme

0.286

1.43

ns

1,3,8 (90-10% of “black”-to-
”white” video transition)

T

SETTLING

Settling time

0.857

ns

1,4,8

VO

Video Channel-to-
Channel output 
skew

0.714

ns

1,5,8

Overshoot/ 
Undershoot

-0.084

+0.084

V

1,6,8 (0.7V full-scale voltage step)

Noise Injection 
Ratio

2.5

%

T

F

Fall Time

--

80% of minimum pixel clock 
period

ns

T

R

Rise Time

--

80% of minimum pixel clock 
period

ns

--

Overshoot/Undershoot

--

30% of high level signal 
voltage range

mA

1

--

Jitter (measured 
between Hsync pulses)

--

One half of the difference 
between max and min interval 
<15% of the pixel clock, DC to 
max.

V

2