Intel E3815 FH8065301567411 Data Sheet

Product codes
FH8065301567411
Page of 5308
 
Electrical Specifications
Intel
®
 Atom™ Processor E3800 Product Family
Datasheet
169
NOTES:
1.
Based on trace length of 0.25”–4”, 2–5 pF Far End Load for Port 0 AND 2–10 pF Far End Load (for Port 1 
and Board impedance of 25–75 Ω. 
2.
Minimum time deviates from SDIO Specification 2.0, minimum time is not defined in specification. 
3.
Measured from 0.58–1.27V.
4.
Takes into consideration EMI filter of 10 pF - 40 Ω -10 pF.
T
ODLY(SDR25)
SD_CLK Rising Edge 
to SDIO_D 
3
11.9
ns
T
ODLY(SDR12)
SD_CLK Falling Edge 
to SDIO_D 
0
11.9
ns
T
SU_SOC 
(DDR)
SoC setup time  
(data valid before 
clock launched)
1
ns
 (For DDR50 Mode)
T
SU_SOC 
(SDR)
SoC setup time  
(data valid before 
clock launched)
4
ns
 (For SDR12/25 
Mode)
T
HD_SOC 
(DDR)
SoC hold time  
(data valid after clock 
launched)
2
ns
 (For DDR50 Mode)
T
HD_SOC 
(SDR)
SoC hold time  
(data valid after clock 
launched)
2
ns
 (For SDR12/25 
Mode)
T
RISE CLK/
T
FALL CLK 
(1.8V)
Clock Rise and Fall 
Time (1.8V 
operation)
1
3
ns
1, 2, 
3, 4
T
RISE CLK/
T
FALL CLK 
(3.3V)
Clock Rise and Fall 
Time (3.3V 
operation)
1
3
ns
1, 2, 
3, 4
Table 122.
SDIO AC Specification
Symbol
Parameter
Min.
Max.
Unit
Figure
Notes
Figure 47. SDIO Timing Diagram (DDR50)
T
WC DDR50
DATA
DATA
DATA
INPUT
OUTPUT
DATA
DATA
DATA
INVALID
min (V
IH
)
max (V
IL
)
min (V
OH
)
max (V
OL
)
min (V
IH
)
max (V
IL
)
T
SU_SOC
T
HD_SOC
T
SU_SOC
T
HD_SOC
T
ODLY(DDR50) - MIN
CLK
T
ODLY(DDR50) - MAX
T
ODLY(DDR50) - MAX
T
ODLY(DDR50) - MIN