Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Electrical Specifications
Intel
®
Atom™ Processor E3800 Product Family
Datasheet
171
9.6.10
SCC - eMMC 4.5 AC Specification
9.6.10.1
HS/DDR Mode AC Characteristics
Figure 50. SDIO Input Timing Diagram (SDR12/25)
Table 123. eMMC 4.5 AC Characteristics (Sheet 1 of 2)
Symbol
Parameter
Min.
Max.
Units
Figures
Notes
F
pp
Clock Frequency Data transfer Mode
200
MHZ
T
wc(HS/DDR)
CLK Cycle Time (High Speed Mode and
DDR Modes)
DDR Modes)
20
–
ns
T
DC
CLK Duty Cycle
40
55
%
T
ODLY(HS)
EMMC_CLK Rising Edge to EMMC_D
(High Speed Mode)
-
13.7
ns
T
ODLY(DDR)
EMMC_CLK Rising Edge to EMMC_D
(DDR Mode)
1.5
7
ns
T
SU(HS)
EMMC_D Input Setup Time to EMMC_CLK
Rising Edge (data read - HS mode)
Rising Edge (data read - HS mode)
1.5
–
ns
T
H(HS)
EMMC_D Input Hold Time to EMMC_CLK
Rising Edge (data read - HS mode)
Rising Edge (data read - HS mode)
3
–
ns
T
SU(DDR)
EMMC_D Input Setup Time to EMMC_CLK
Rising Edge
Rising Edge
(data read - DDR Mode)
2.5
–
ns
T
H(DDR)
EMMC_D Input Setup Time to EMMC_CLK
Rising Edge (data read–DDR Mode)
Rising Edge (data read–DDR Mode)
2.5
–
ns
T
RISE(HS)
Rise Time (Output - HS mode)
-
3
ns
1, 2, 3
T
FALL(HS)
Fall Time (Output -HS mode)
-
3
ns
1, 2, 3
T
RISE(DDR)
Rise Time (Output - DDR mode)
-
2
ns
1, 2, 3
CLK
DATA/CMD
T
SU_SOC
T
HD_SOC
V
IH
V
IL
½ V
DD