Intel E3815 FH8065301567411 Data Sheet

Product codes
FH8065301567411
Page of 5308
 
Intel
®
 Atom™ Processor E3800 Product Family
Datasheet
1757
Default: 00000080h
16.5.10
Interrupt Register (INTERRUPTREG)—Offset 3Ch
Access Method
Default: 00000100h
Type: 
PCI Configuration Register
(Size: 32 bits)
Offset: 
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0
Re
se
rv
ed
0
CA
PPTR_PO
WE
R
Bit 
Range
Default & 
Access
Field Name (ID): Description
31:8
000000h
RO
Reserved0: 
Reserved.
7:0
80h
RO
Capabilities Pointer (CAPPTR_POWER): 
Indicates what the next capability is. This 
capability can be programmed to be PM Capability (0x80) if PM Capability is enabled in 
SB. When PM capability is disabled, this register is 00h.
Type: 
PCI Configuration Register
(Size: 32 bits)
Offset: 
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0
MAX
_
LA
T
MI
N
_
G
N
T
Re
se
rv
ed
0
INTPIN
IN
T
LINE
Bit 
Range
Default & 
Access
Field Name (ID): Description
31:24
00h
RO
Max_Lat (MAX_LAT): 
Value of 0 indicates that the device has no major requirements 
for the settings of latency timers.
23:16
00h
RO
Min_Gnt (MIN_GNT): 
Value of 0 indicates that the device has no major requirements 
for the settings of latency timers.
15:12
0h
RO
Reserved0: 
Reserved.
11:8
1h
RO
Interrupt Pin (INTPIN): 
Each AHB IP on Bridge is a single function device. Hence 
Bridge only generates INTA on IOSF SB. The Fabric on AHB Bridge appears as a 
Multifunction device. Interrupt Pin Value in this register is reflected from the IPIN value 
in the private configuration space.
7:0
00h
RW
Interrupt Line (INTLINE): 
Bridge does not use this field directly. It is used to 
communicate to software the interrupt line that the interrupt pin is connected to.