Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
1776
Datasheet
16.6.13
Host Control 1 Register (HOST_CTL)—Offset 28h
Access Method
Default: 00h
1
0b
RO
Command Inhibit (DAT) (cmd_inhibit_dat):
This status bit is generated if either the
DAT Line Active or the Read Transfer Active is set to 1. If this bit is 0, it indicates the
Host Controller can issue the next SD Command. Commands with busy signal belong to
Command Inhibit (DAT) (ex. R1b, R5b type). Changing from 1 to 0 generates a Transfer
Complete interrupt in the Normal Interrupt Status register. Note: The SD Host Driver
can save registers in the range of 000-00Dh for a suspend transaction after this bit has
changed from 1 to 0.
•
•
1 Cannot issue command which uses the DAT line
•
0 Can issue command which uses the DAT line
0
0b
RO
Command Inhibit (CMD) (cmd_inhibit_cmd):
Command Inhibit (CMD) If this bit is
0, it indicates the CMD line is not in use and the Host Controller can issue a SD
Command using the CMD line. cleared when the command response is received. Auto
CMD12 and Auto CMD23 consist of two responses. In this case, this bit is not cleared by
the response of CMD12 or CMD23 but cleared by the response of a read/write
command. Status issuing Auto CMD12 is not read from this bit. So if a command is
issued during Auto CMD12 operation, Host Controller shall manage to issue two
commands: CMD12 and a command set by Command register. Even if the Command
Inhibit (DAT) is set to 1, commands using only the CMD line can be issued if this bit is 0.
Changing from 1 to 0 generates a Command Complete Interrupt in the Normal Interrupt
Status register. If the Host Controller cannot issue the command because of a command
conflict error (Refer to Command CRC Error in Section 2.2.18) or because of Command
Not Issued By Auto CMD12 Error (Refer to Section 2.2.23), this bit shall remain 1 and
the Command Complete is not set.
•
•
1 Cannot issue command
•
0 Can issue command using only CMD line
Bit
Range
Default &
Access
Field Name (ID): Description
Type:
Memory Mapped I/O Register
(Size: 8 bits)
Offset:
BAR Type:
PCI Configuration Register (Size: 32 bits)
BAR Reference:
[B:0, D:17, F:0] + 10h
7
4
0
0
0
0
0
0
0
0
0
cr
d_de
t_sig
_
se
l
cr
d_de
t_tst
_
lvl
sd8_bit_m
od
e
dma_se
l
hi_spd_e
n
dat
a
_t
x_w
id
led_c
tl
Bit
Range
Default &
Access
Field Name (ID): Description
7
0b
RW
Card Detect Signal Selection (crd_det_sig_sel):
This bit selects source for the card
detection.
•
•
1 = The Card Detect Test Level is selected (for test purposes)
•
0 = SDCD# is selected (for normal use)
When the source for the card detection is switched, the interrupt should be disabled
during the switching period by clearing the Interrupt Status/Signal Enable register in
order to mask unexpected interrupt being caused by the glitch. The Interrupt Status/
Signal Enable should be disabled during the period of debouncing.