Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
Datasheet
1777
16.6.14
Power Control Register (PWR_CTL)—Offset 29h
Access Method
Default: 00h
6
0b
RW
Card Detect Test Level (crd_det_tst_lvl):
This bit is enabled while the Card Detect
Signal Selection is set to 1, and it indicates whether or not the card is inserted.
•
•
1 = Card Inserted
•
0 = No Card
5
0b
RW
SD8 Bit Mode (sd8_bit_mode):
This bit selects the data width of the HC. The HD
shall select it to match the data width of the SD card.
4:3
00b
RW
DMA Select (dma_sel):
One of supported DMA modes can be selected. The host driver
shall check support of DMA modes by referring the Capabilities register. Use of selected
DMA is determined by DMA Enable of the Transfer Mode register.
•
•
00 = SDMA is selected
•
01 = Reserved (New assignment is not allowed)
•
10 = 32-bit Address ADMA2 is selected
•
11 = Reserved (will be modified by Version 4.00)
2
0b
RW
High Speed Enable (hi_spd_en):
This bit is optional. Before setting this bit, the Host
Driver shall check the High Speed Support in the Capabilities register. If this bit is set to
0 (default), the Host Controller outputs CMD line and DAT lines at the falling edge of the
SD Clock (up to 25MHz). If this bit is set to 1, the Host Controller outputs CMD line and
DAT lines at the rising edge of the SD Clock (up to 50MHz). If Preset Value Enable in the
Host Control 2 register is set to 1, Host Driver needs to reset SD Clock Enable before
changing this field to avoid generating clock glitches. After setting this field, the Host
Driver sets SD Clock Enable again.
•
•
1 = 4-bit mode
•
0 = 1-bit mode
1
0b
RW
Data Transfer Width (data_tx_wid):
Reserved.
0
0b
RW
LED Control (led_ctl):
This bit selects the data width of the Host Controller. The Host
Driver shall set it to match the data width of the SD card.
•
•
1 = 4-bit mode
•
0 = 1-bit mode
Bit
Range
Default &
Access
Field Name (ID): Description
Type:
Memory Mapped I/O Register
(Size: 8 bits)
Offset:
BAR Type:
PCI Configuration Register (Size: 32 bits)
BAR Reference:
[B:0, D:17, F:0] + 10h
7
4
0
0
0
0
0
0
0
0
0
rs
vd
hw_
rs
t
sd_bus
_v
olt_sel
sd_bus
_pwr
Bit
Range
Default &
Access
Field Name (ID): Description
7:5
0h
RO
Rsvd (rsvd):
Reserved.