Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
1780
Datasheet
Default: 00h
16.6.17
Clock Control Register (CLK_CTL)—Offset 2Ch
At the initialization of the Host Controller, the Host Driver shall set the SDCLK
Frequency Select according to the Capabilities register.
Access Method
Default: 0000h
Type:
Memory Mapped I/O Register
(Size: 8 bits)
Offset:
BAR Type:
PCI Configuration Register (Size: 32 bits)
BAR Reference:
[B:0, D:17, F:0] + 10h
7
4
0
0
0
0
0
0
0
0
0
rs
vd
wak
eup_e
n
_
sd_r
m
w
ak
eu
p
_en_sd_ins
wa
ke
up
_
en
_
cr
d
_
in
t
Bit
Range
Default &
Access
Field Name (ID): Description
7:3
0h
RO
Reserved (rsvd):
Reserved.
2
0b
RW
Wakeup Event Enable On SD Card Removal (wakeup_en_sd_rm):
This bit
enables wakeup event via Card Removal assertion in the Normal Interrupt Status
register. FN_WUS (Wake Up Support) in CIS does not affect this bit.
•
•
1 = Enable
•
0 = Disable
1
0b
RW
Wakeup Event Enable On SD Card Insertion (wakeup_en_sd_ins):
This bit
enables wakeup event via Card Insertion assertion in the Normal Interrupt Status
register. FN_WUS (Wake Up Support) in CIS does not affect this bit.
•
•
1 = Enable
•
0 = Disable
0
0b
RW
Wakeup Event Enable On Card Interrupt (wakeup_en_crd_int):
This bit enables
wakeup event via Card Interrupt assertion in the Normal Interrupt Status register. This
bit can be set to 1 if FN_WUS (Wake Up Support) in CIS is set to 1.
•
•
1 = Enable
•
0 = Disable
Type:
Memory Mapped I/O Register
(Size: 16 bits)
Offset:
BAR Type:
PCI Configuration Register (Size: 32 bits)
BAR Reference:
[B:0, D:17, F:0] + 10h