Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
Datasheet
1781
15
12
8
4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
sd
cl
k_
fr
eq
_
se
l
u
ppe
r_s
d
clk_fr
eq
_sel
rs
vd
sd_c
lk_e
n
in
t_clk_stab
le
int_c
lk_e
n
Bit
Range
Default &
Access
Field Name (ID): Description
15:8
00h
RW
SDCLK Frequency Select (sdclk_freq_sel):
This register is used to select the
frequency of the SDCLK pin. The definition of this field is dependent on the Host
Controller Version. (1) 8-bit Divided Clock Mode This mode is supported by the Host
Controller Version 1.00 and 2.00. The frequency is not programmed directly, rather, this
register holds the divisor of the Base Clock Frequency For SD Clock in the capabilities
register. Only the following settings are allowed. (1) 8-bit Divided Clock Mode
•
•
80h = base clock divided by 256
•
40h = base clock divided by 128
•
20h = base clock divided by 64
•
10h = base clock divided by 32
•
08h = base clock divided by 16
•
04h = base clock divided by 8
•
02h = base clock divided by 4
•
01h = base clock divided by 2
•
00h = base clock(10MHz and up)
Setting 00h specifies the highest frequency of the SD Clock. When setting multiple bits,
the most significant bit is used as the divisor, but it should not be set. The three default
divider values can be calculated by the frequency that is defined by the Base Clock
Frequency For SD Clock in the Capabilities register.
•
•
400KHz divider value
•
25MHz divider value
•
50MHz divider value
According to the Physical Layer Specification, the maximum SD Clock frequency is 25
MHz in normal speed mode and 50MHz in high speed mode, and shall never exceed this
limit. The frequency of the SDCLK is set by the following formula: Clock Frequency =
(Base Clock) / divisor Thus, choose the smallest possible divisor which results in a clock
frequency that is less than or equal to the target frequency. For example, if the Base
Clock Frequency For SD Clock in the Capabilities register has the value 33MHz, and the
target frequency is 25MHz, then choosing the divisor value of 01h will yield 16.5MHz,
which is the nearest frequency less than or equal to the target. Similarly, to approach a
clock value of 400KHz, the divisor value of 40h yields the optimal clock value of 258KHz.
(2) 10-bit Divided Clock Mode
Host Controller Version 3.00 supports this mandatory
mode instead of the 8-bit Divided Clock Mode. The length of divider is extended to 10
bits, and all divider values shall be supported.
•
•
3FFh = 1/2046 Divided Clock
•
N = 1/2N Divided Clock (Duty 50%)
•
002h = 1/4 Divided Clock
•
001h = 1/2 Divided Clock
•
000h = Base Clock (10MHz and up)
•
3FFh = Base Clock * M / 1024
•
...... .......................
•
N - 1 = Base Clock * M / N
•
...... .......................
•
002h = Base Clock * M / 3
•
001h = Base Clock * M / 2
•
000h = Base Clock * M
This field depends on setting of Preset Value Enable in the Host Control 2 register. If
Preset Value Enable = 0, this field is set by Host Driver. If the Preset Value Enable = 1,
this field is automatically set to a value specified in one of Preset Value registers.