Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
1784
Datasheet
16.6.20
Normal Interrupt Status Register (NML_INT_STATUS)—Offset
30h
The Normal Interrupt Status Enable affects reads of this register, but Normal Interrupt
Signal Enable does not affect these reads. An interrupt is generated when the Normal
Interrupt Signal Enable is enabled and at least one of the status bits is set to 1. Writing
1 to a bit of RW1C attribute clears it; writing 0 keeps the bit unchanged. Writing 1 to a
bit of ROC attribute keeps the bit unchanged. More than one status can be cleared with
a single register write. The Card Interrupt is cleared when the card stops asserting the
interrupt; that is, when the Card Driver services the interrupt condition.
Access Method
2
0b
RW
Software Reset For DAT Line (sw_rst_dat_ln):
Only part of data circuit is reset.
DMA circuit is also reset. The following registers and bits are cleared by this bit: Buffer
Data Port register
•
•
Buffer is cleared and initialized.
Present State register
•
•
Buffer Read Enable
•
Buffer Write Enable
•
Read Transfer Active
•
Write Transfer Active
•
DAT Line Active
•
Command Inhibit (DAT)
Block Gap Control register
•
•
Continue Request
•
Stop At Block Gap Request
Normal Interrupt Status register
•
•
Buffer Read Ready
•
Buffer Write Ready
•
DMA Interrupt
•
Block Gap Event
•
Transfer Complete
•
1 = Reset
•
0 = Work
When Auto or Dynamic Clock Gating is enabled for this controller, the Software Reset bit
may require several reads before the bit clears.
1
0b
RW
Software Reset For CMD Line (sw_rst_cmd_ln):
Only part of command circuit is
reset. The following registers and bits are cleared by this bit: Present State register
•
•
Command Inhibit (CMD)
Normal Interrupt Status register
•
•
Command Complete
•
1 = Reset
•
0 = Work
When Auto or Dynamic Clock Gating is enabled for this controller, the Software Reset bit
may require several reads before the bit clears.
0
0b
RW
Software Reset For All (sw_rst_all):
This reset affects the entire Host Controller
except for the card detection circuit. Register bits of type ROC, RW, RW1C, RWAC are
cleared to 0. During its initialization, the Host Driver shall set this bit to 1 to reset the
Host Controller. The Host Controller shall reset this bit to 0 when Capabilities registers
are valid and the Host Driver can read them. Additional use of Software Reset For All
may not affect the value of the Capabilities registers. If this bit is set to 1, the host
driver should issue reset command and reinitialize the SD card.
•
•
1 = Reset
•
0 = Work
When Auto or Dynamic Clock Gating is enabled for this controller, the Software Reset bit
may require several reads before the bit clears.
Bit
Range
Default &
Access
Field Name (ID): Description