Intel E3815 FH8065301567411 Data Sheet

Product codes
FH8065301567411
Page of 5308
 
Intel
®
 Atom™ Processor E3800 Product Family
Datasheet
1789
16.6.22
Normal Interrupt Status Enable (NRM_INT_STATUS_EN)—
Offset 34h
Setting to 1 enables Interrupt Status. Implementation Note: The Host Controller 
may sample the card interrupt signal during interrupt period, and may hold its value in 
the flip-flop. If the Card Interrupt Status Enable is set to 0, the Host Controller shall 
clear all internal signals regarding Card Interrupt.
Access Method
Default: 0000h
3
0b
RW
Command Index Error (cmd_index_err): 
This bit is set if a Command Index error 
occurs in the command response. 
1 = error 
0 = no error 
2
0b
RW
Command End Bit Error (cmd_end_bit_err): 
This bit is set when detecting that the 
end bit of a command response is 0. 
1 = End Bit Error generated 
0 = no error 
1
0b
RW
Command CRC Error (cmd_crc_err): Command CRC Error
 is generated in two 
cases. If a response is returned and the Command Timeout Error is set to 0(indicating 
no timeout), this bit is set to 1 when detecting a CRC error in the command response. 
The Host Controller detects a CMD line conflict by monitoring the CMD line when a 
command is issued. If the Host Controller drives the CMD line to 1 level, but detects 0 
level on the CMD line at the next SD clock edge, then the Host Controller shall abort the 
command (Stop driving CMD line) and set this bit to 1. The Command Timeout Error 
shall also be set to 1 to distinguish CMD line conflict (refer to tabular data in the spec. 
that explains the relationship between Command CRC Error and Command Timeout 
Error
). 
1 = CRC Error Generated. 
0 = no error 
0
0b
RW
Command Timeout Error (cmd_timeout_err): 
This bit is set only if no response is 
returned within 64 SD clock cycles from the end bit of the command. If the Host 
Controller detects a CMD line conflict (in which case Command CRC Error shall also be 
set, as shown in tabular data in the spec that explains the relationship between this bit 
and Command CRC Error) this bit shall be set without waiting for 64 SD clock cycles, 
because the command will be aborted by the Host Controller. 
1 = time out 
0  =  no  Error 
Bit 
Range
Default & 
Access
Field Name (ID): Description
Type: 
Memory Mapped I/O Register
(Size: 16 bits)
Offset: 
BAR Type: 
PCI Configuration Register (Size: 32 bits)
BAR Reference: 
[B:0, D:17, F:0] + 10h
15
12
8
4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
fi
xe
d_0
rsvd
b
oo
t_ter
m_in
t_en
boot_ack_r
cv_en
cr
d
_
in
t_
st
at
_
en
crd_rm_stat_en
cr
d_ins
_
stat_e
n
buf_rd_rdy_stat_en
bu
f_wr
_r
dy
_s
ta
t_en
d
m
a_int
_
stat_en
blk_g
ap_e
vent
_
stat_e
n
tx_comp_stat_en
cmd_comp
_stat_e
n