Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
1790
Datasheet
16.6.23
Error Interrupt Status Enable Register (ERR_INT_STAT_EN)—
Offset 36h
Setting to 1 enables interrupt status. Implementation Note: To detect CMD line
conflict, the Host Driver must set both Command Timeout Error Status Enable and
Command CRC Error Status Enable to 1.
Access Method
Bit
Range
Default &
Access
Field Name (ID): Description
15
0b
RO
Fixed to 0 (fixed_0):
The Host Driver shall control error interrupts using the Error
Interrupt Status Enable register.
14:11
0h
RO
Reserved (rsvd):
Reserved.
10
0b
RW
Boot Term Interrupt Enable (boot_term_int_en):
0 = Masked.
9
0b
RW
Boot Acknowledge Receive Enable (boot_ack_rcv_en):
0 = Masked
8
0b
RW
Card Interrupt Status Enable (crd_int_stat_en):
If this bit is set to 0, the Host
Controller shall clear interrupt request to the System. The Card Interrupt detection is
stopped when this bit is cleared, and restarted when this bit is set to 1. The Host Driver
may clear the Card Interrupt Status Enable before servicing the Card Interrupt, and
may set this bit again after all interrupt requests from the card are cleared, to prevent
inadvertent interrupts.
•
•
1 = enabled
•
0 = masked
7
0b
RW
Card Removal Status Enable (crd_rm_stat_en):
•
•
1 = enabled
•
0 = masked
6
0b
RW
Card Insertion Status Enable (crd_ins_stat_en):
[
•
1 = enabled
•
0 = masked
5
0b
RW
Buffer Read Ready Status Enable (buf_rd_rdy_stat_en):
•
•
1 = enabled
•
0 = masked
4
0b
RW
Buffer Write Ready Status Enable (buf_wr_rdy_stat_en):
•
•
1 = enabled
•
0 = masked
3
0b
RW
DMA Interrupt Status Enable (dma_int_stat_en):
•
•
1 = enabled
•
0 = masked
2
0b
RW
Block Gap Event Status Enable (blk_gap_event_stat_en):
•
•
1 = enabled
•
0 = masked
1
0b
RW
Transfer Complete Status Enable (tx_comp_stat_en):
•
•
1 = enabled
•
0 = masked
0
0b
RW
Command Complete Status Enable (cmd_comp_stat_en):
•
•
1 = enabled
•
0 = masked