Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
Datasheet
1803
Default: 00h
16.6.36
Shared Bus Control Register (SHARED_BUS)—Offset E0h
This register is optional. The devices on shared bus are not intended to be controlled by
the Standard Host Driver. This is because shared bus configuration depends on a host
system; the devices on shared bus may be controlled by a specific driver of a host
system.
Access Method
Default: 00000000h
Type:
Memory Mapped I/O Register
(Size: 8 bits)
Offset:
BAR Type:
PCI Configuration Register (Size: 32 bits)
BAR Reference:
[B:0, D:17, F:0] + 10h
7
4
0
0
0
0
0
0
0
0
0
rs
vd
de
bu
g
_
se
l
Bit
Range
Default &
Access
Field Name (ID): Description
7:1
00h
RO
Reserved (rsvd):
Reserved.
0
0b
WO
Debug Select (debug_sel):
•
•
1 = cmd register, interrupt status, transmitter module, ahb_iface module and clk
sdcard signals are probed out.
•
0 = receiver module and fifo_ctrl module signals are probed out
Type:
Memory Mapped I/O Register
(Size: 32 bits)
Offset:
BAR Type:
PCI Configuration Register (Size: 32 bits)
BAR Reference:
[B:0, D:17, F:0] + 10h
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RS
VD0
pwr_c
trl
RS
VD1
int_pin
RS
VD2
clk_p
in
RS
VD3
bus
_
w
id
th
RS
VD4
num_int_p
in
RS
VD5
num_clk_pin
Bit
Range
Default &
Access
Field Name (ID): Description
31
0b
RO
RSVD0:
Reserved