Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
1810
Datasheet
16.7.5
Base Address Register (BAR)—Offset 10h
Each AHB device is a single function device with only a single BAR associated with it.
Bits 31:4 indicate the Base Address register. Power-up software can determine how
much address space the AHB Device requires by writing a value of all 1's to the register
and then reading the value back. Bridge will return 0's in all don't-care address bits,
effectively specifying the address space required. Unimplemented Base Address
registers are hardwired to zero. This is the Size Indicator Read only bits of the register.
Access Method
Default: 00000000h
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Re
se
rv
ed
0
MULFNDEV
HE
AD
E
R
T
Y
PE
LA
TT
IMER
CA
CH
ELI
N
E
_
SI
ZE
Bit
Range
Default &
Access
Field Name (ID): Description
31:24
00h
RO
Reserved0:
Reserved.
23
0h
RO
Multifunction Device (MULFNDEV):
This bit is always 0 for non-fabric ports. For
fabric ports it is driven from the fabric_mult_function strap. A value of 1 indicates a
multifunction device; a value of 0 indicates a single function device.
22:16
00h
RO
Header Type (HEADERTYPE):
Implements Type 0 Configuration header.
15:8
00h
RO
Latency Timer (LATTIMER):
Doesnt apply to PCI Express. Hardwired to 00h.
7:0
00h
RW
Cache Line Size (CACHELINE_SIZE):
Doesnt apply to PCI Express. PCI Express spec
requires this to be implemented as a R/W register but has no functional impact on the
AHB Device connected.
Type:
PCI Configuration Register
(Size: 32 bits)
Offset:
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
B
ASE
A
D
D
R
S
IZE
IND
ICA
TO
R
PREFE
TC
H
A
B
LE
TY
PE
ME
S
S
A
G
E_
SP
AC
E
Bit
Range
Default &
Access
Field Name (ID): Description
31:12
00000h
RW
Base Address (BASEADDR):
Base address of the AHB device memory space. Taken
from Strap values as 1s.