Intel E3815 FH8065301567411 Data Sheet

 

Intel

®

 Atom™ Processor E3800 Product Family

Datasheet

1815

Default: 00000000h

31:16

0000h

RO

Reserved.

15

0h

RW/1C

0 = Software clears the bit by writing a 1 to it. 

1 = This bit is set when the AHB Device would normally assert the PME# signal 

independent of the state of the PME Enable bit in this register.

14:9

00h

RO

Reserved.

8

0h

RW

A 1 enables the function to assert PME#. When 0, PME# 

message on SB is disabled.

7:4

0h

RO

Reserved.

3

1h

RO

This bit indicates that devices transitioning from 

D3hot to D0 because of PowerState commands do not perform an internal reset. 

Configuration Context is preserved.

2

0h

RO

Reserved.

1:0

0h

RW

This field is used both to determine the current power 

state of the AHB IP and to set a new power state. The values are: 

00 = D0 state 

11 = D3HOT state 

Others = Reserved 

Notes: If software attempts to write a value of 01b or 10b in to this field, the write 

operation must complete normally; however, the data is discarded and no state change 

occurs. When in the D3HOT states, interrupts are blocked. D3Hot will not be used for 

upstream decode on fabric ports.

PCI Configuration Register

(Size: 32 bits)

31

28

24

20

16

12

8

4

0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

GEN_RE

G

_

RW1

31:0

00000000h

RW

capabilities over-ride for the sd/sdio/emmc host controler (bits 31:0)