Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
Datasheet
1825
16.8.6
Command Register (CMD)—Offset Eh
The Host Driver shall check the Command Inhibit (DAT) bit and Command Inhibit
(CMD) bit in the Present State register before writing to this register. Writing to the
upper byte of this register triggers SD command generation. The Host Driver has the
responsibility to write this register because the Host Controller does not protect for
writing when Command Inhibit (CMD) is set.
Access Method
Default: 0000h
Type:
Memory Mapped I/O Register
(Size: 16 bits)
Offset:
BAR Type:
PCI Configuration Register (Size: 32 bits)
BAR Reference:
[B:0, D:18, F:0] + 10h
15
12
8
4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
rs
vd
cmd_ind
ex
cm
d_ty
pe
da
ta
_p
r_
se
l
cm
d
_
index_chk_en
cmd_cr
c_chk_e
n
re
se
rv
ed
re
sp
_typ
e_s
el
Bit
Range
Default &
Access
Field Name (ID): Description
15:14
0h
RO
Rsvd (rsvd):
Reserved.
13:8
0h
RW
Command Index (cmd_index):
These bits shall be set to the command number
(CMD0-63, ACMD0-63) that is specified in bits 45-40 of the Command-Format in the
Physical Layer Specification and SDIO Card Specification.
7:6
00b
RW
Command Type (cmd_type):
There are three types of special commands: Suspend,
Resume and Abort. These bits shall be set to 00b for all other commands. (1) Suspend
Command
If the Suspend command succeeds, the Host Controller shall assume the SD
Bus has been released and that it is possible to issue the next command, which uses the
DAT line. The Host Controller shall de-assert Read Wait for read transactions and stop
checking busy for write transactions. The interrupt cycle shall start, in 4-bit mode. If the
Suspend command fails, the Host Controller shall maintain its current state, and the
Host Driver shall restart the transfer by setting Continue Request in the Block Gap
Control register. (Refer to 3.12.1 Suspend Sequence). (2) Resume Command The
Host Driver re-starts the data transfer by restoring the registers in the range of 000-
00Dh. (Refer to Figure 1-4 in section 1.6 for the register map.) The Host Controller shall
check for busy before starting write transfers. (3) Abort Command If this command is
set when executing a read transfer, the Host Controller shall stop reads to the buffer. If
this command is set when executing a write transfer, the Host Controller shall stop
driving the DAT line. After issuing the Abort command, the Host Driver should issue a
software reset. (Refer to 3.8 Abort Transaction).
•
•
11b = Abort -- CMD12, CMD52 for writing 'I/O Abort' in CCCR
•
10b = Resume -- CMD52 for writing 'Function Select' in CCCR
•
01b = Suspend -- CMD52 for writing 'Bus Suspend' in CCCR
•
00b = Normal -- Other commands
5
0b
RW
Data Present Select (data_pr_sel):
This bit is set to 1 to indicate that data is present
and shall be transferred using the DAT line. It is set to 0 for the following: (1)
Commands using only CMD line (ex. CMD52). (2) Commands with no data transfer but
using busy signal on DAT[0] line (R1b or R5b ex. CMD38). (3) Resume command.
•
•
1 = Data Present
•
0 = No Data Present