Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
1826
Datasheet
16.8.7
Response Register 0 (RESPONSE0)—Offset 10h
This register is used to store responses from SD cards.
Access Method
Default: 00000000h
16.8.8
Response Register 2 (RESPONSE2)—Offset 14h
This register is used to store responses from SD cards.
Access Method
4
0b
RW
Command Index Check Enable (cmd_index_chk_en):
If this bit is set to 1, the
Host Controller shall check the Index field in the response to see if it has the same value
as the command index. If it is not, it is reported as a Command Index Error. If this bit is
set to 0, the Index field is not checked.
•
•
1 = Enable
•
0 = Disable
3
0b
RW
Command CRC Check Enable (cmd_crc_chk_en):
If this bit is set to 1, the Host
Controller shall check the CRC field in the response. If an error is detected, it is reported
as a Command CRC Error. If this bit is set to 0, the CRC field is not checked. The position
of CRC field is determined according to the length of the response. (Refer to definition in
D01-00 and Table 2-10 below.)
•
•
1 = Enable
•
0 = Disable
2
0b
RO
Reserved (reserved):
Reserved.
1:0
0h
RW
Response Type Select (resp_type_sel):
•
•
00 = No Response
•
01 = Response Length 136
•
10 = Response Length 48
•
11 = Response Length 48 check Busy after response
Bit
Range
Default &
Access
Field Name (ID): Description
Type:
Memory Mapped I/O Register
(Size: 32 bits)
Offset:
BAR Type:
PCI Configuration Register (Size: 32 bits)
BAR Reference:
[B:0, D:18, F:0] + 10h
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
cmd_re
sp
Bit
Range
Default &
Access
Field Name (ID): Description
31:0
0h
RO
Command Response (cmd_resp):
The Table 2-12 describes the mapping of
command responses from the SD Bus to this register for each response type. In the
table, R[] refers to a bit range within the response data as transmitted on the SD Bus,
REP[] refers to a bit range within the Response register