Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
1834
Datasheet
16.8.15
Block Gap Control Register (_BLK_GAP_CTL)—Offset 2Ah
Access Method
Default: 00h
4
0b
RW
HW Reset (hw_rst):
Reserved.
3:1
0h
RW
SD Bus Voltage Select (sd_bus_volt_sel):
By setting these bits, the Host Driver
selects the voltage level for the SD card. Before setting this register, the Host Driver
shall check the Voltage Support bits in the Capabilities register. If an unsupported
voltage is selected, the Host System shall not supply SD Bus voltage.
•
•
111b = 3.3V (Typ.)
•
110b = 3.0V (Typ.)
•
101b = 1.8V (Typ.)
•
100b 000b Reserved
0
0b
RW
SD Bus Power (sd_bus_pwr):
Before setting this bit, the SD Host Driver shall set SD
Bus Voltage Select. If the Host Controller detects the No Card state, this bit shall be
cleared. If this bit is cleared, the Host Controller shall immediately stop driving CMD and
DAT[3:0] (tri-state) and drive SDCLK to low level (Refer to Section 2.2.14) For SD
Controller, this bit controls the bus voltage to SDMMC3. For SDIO Controller, power to
SDIO device on SDMMC2 is not controlled by this bit. GPIO register and pin can be used
to controller the SDIO device power. For eMMC Controller, power to eMMC device on
SDMMC1 is not controlled by this bit. GPIO register and pin or alternative solutions can
be used.
•
•
1 = Power on
•
0 = Power off
Bit
Range
Default &
Access
Field Name (ID): Description
Type:
Memory Mapped I/O Register
(Size: 8 bits)
Offset:
BAR Type:
PCI Configuration Register (Size: 32 bits)
BAR Reference:
[B:0, D:18, F:0] + 10h
7
4
0
0
0
0
0
0
0
0
0
rsvd
dr
iv
e_c
csd
int_blk_gap
rd_w
ait_c
tl
cont
_
req
st
p_b
lk_gap
_
re
q
Bit
Range
Default &
Access
Field Name (ID): Description
7:5
0h
RO
Reserved (rsvd):
Reserved.
4
0b
RW
DRIVE_CCSD (drive_ccsd):
If the driver set this bit (change from ???0??? to
???1???), Host controller will send command completion.